M30280F6HP#D3 Renesas Electronics America, M30280F6HP#D3 Datasheet - Page 314
M30280F6HP#D3
Manufacturer Part Number
M30280F6HP#D3
Description
MCU 3/5V 48K I-TEMP 80-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheet
1.M30280F6HPU9.pdf
(425 pages)
Specifications of M30280F6HP#D3
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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M
R
R
e
E
1
Figure 17.9 PCR Register
Figure 17.10 PACR Register
. v
J
6
0
C
2
9
2 /
0 .
B
0
0
8
0
Pin Assignment Control Register
NOTE:
Port Control Register
G
4
b7
b7
J
7
a
o r
1. Set the PACR register by the next instruction after setting the PRC2 bit in the PRCR register to "1"(write
0 -
. n
b6
b6
u
enable).
2
3
p
0
b5
, 1
b5
0
(
M
2
b4
b4
0
1
0
6
b3
7
b3
C
2 /
b2
b2
page 292
, 8
b1
b1
M
1
b0
b0
6
C
Bit Symbol
Bit Symbol
2 /
f o
U1MAP
PACR0
PACR1
PACR2
(b6-b3)
Symbpl
Symbpl
PCR
PCR0
(b7-b1)
PACR
8
3
) B
8
5
(1)
Pin enabling bit
Reserved bits
UART1 pin remapping bit
Port P1 control bit
Nothing is assigned.
content is "0".
Address
03FF
Address
025D
Bit Name
Bit Name
16
16
When write, set to "0". When read, its
After Reset
00
UART1 pins assigned to
0 : P6
1 : P7
After Reset
00
010 : 64 pin
011 : 80 pin
All other values are reserved. Do
not use.
Nothing is assigned.
set to “0”. When read, its
content is “0”.
16
Operation performed when the P1
register is read
0: When the port is set for input,
1: The port latch is read
16
the input levels of P1
pins are read. When set for
output, the port latch is read.
regardless of whether the port
is set for input or output.
7
3
to P7
to P6
Function
0
4
Function
17. Programmable I/O Ports
When write,
0
to P1
7
RW
RW
RW
RW
RW
RW
RW
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