M30627FJPGP#D5C Renesas Electronics America, M30627FJPGP#D5C Datasheet - Page 81
M30627FJPGP#D5C
Manufacturer Part Number
M30627FJPGP#D5C
Description
MCU 3/5V 512K 128-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheet
1.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30627FJPGP#D5C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30627FJPGP#D5CM30627FJPGP#U3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 8.4
8.2.6
Shown above is the case where CSEi1W to CSEi0W (i = 0 to 3) bits in the CSE register are “ 00b” (one wait state).
This signal is provided for accessing external devices which need to be accessed at low speed. If input on the
RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in the bus
cycle. While in a wait state, the following signals retain the state in which they were when the RDY signal was
acknowledged.
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA
Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle is
executed. Figure 8.4 shows Example in which the Wait State was Inserted into Read Cycle by RDY Signal. To
use the RDY signal, set the corresponding bit (CS3W to CS0W bits) in the CSR register to “0” (with wait state).
When not using the RDY signal, the RDY pin must be pulled-up.
In an instance of separate bus
In an instance of multiplexed bus
BCLK
RD
RDY
BCLK
RD
RDY
CSi
(i=0 to 3)
CSi
(i=0 to 3)
Jan 10, 2006
RDY Signal
: Wait using RDY signal
: Wait using software
Example in which Wait State was Inserted into Read Cycle by RDY Signal
Page 64 of 390
Accept timing of RDY signal
tsu(RDY - BCLK)
Accept timing of RDY signal
tsu(RDY - BCLK)
8. Bus
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