MC9S08RE16FDE Freescale Semiconductor, MC9S08RE16FDE Datasheet - Page 101
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MC9S08RE16FDE
Manufacturer Part Number
MC9S08RE16FDE
Description
IC MCU 16K FLASH 1K RAM 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08RE16FDE
Core Processor
HCS08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
48-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
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Freescale Semiconductor
LDX #opr8i
LDX opr8a
LDX opr16a
LDX oprx16,X
LDX oprx8,X
LDX ,X
LDX oprx16,SP
LDX oprx8,SP
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
LSR opr8a
LSRA
LSRX
LSR oprx8,X
LSR ,X
LSR oprx8,SP
MOV opr8a,opr8a
MOV opr8a,X+
MOV #opr8i,opr8a
MOV ,X+,opr8a
MUL
NEG opr8a
NEGA
NEGX
NEG oprx8,X
NEG ,X
NEG oprx8,SP
NOP
NSA
ORA #opr8i
ORA opr8a
ORA opr16a
ORA oprx16,X
ORA oprx8,X
ORA ,X
ORA oprx16,SP
ORA oprx8,SP
PSHA
PSHH
PSHX
PULA
PULH
PULX
ROL opr8a
ROLA
ROLX
ROL oprx8,X
ROL ,X
ROL oprx8,SP
Source
Form
Load X (Index Register
Low) from Memory
Logical Shift Left
(Same as ASL)
Logical Shift Right
Move
Unsigned multiply
Negate
(Two’s Complement)
No Operation
Nibble Swap
Accumulator
Inclusive OR Accumulator
and Memory
Push Accumulator onto
Stack
Push H (Index Register
High) onto Stack
Push X (Index Register
Low) onto Stack
Pull Accumulator from
Stack
Pull H (Index Register
High) from Stack
Pull X (Index Register
Low) from Stack
Rotate Left through Carry
Operation
Table 7-2. HCS08 Instruction Set Summary (Sheet 5 of 7)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Push (A); SP ← (SP) – 0x0001
Push (H); SP ← (SP) – 0x0001
Push (X); SP ← (SP) – 0x0001
SP ← (SP + 0x0001); Pull (H)
SP ← (SP + 0x0001); Pull (A)
SP ← (SP + 0x0001); Pull (X)
IX+/DIR and DIR/IX+ Modes
0
C
H:X ← (H:X) + 0x0001 in
(M)
M ← – (M) = 0x00 – (M)
M ← – (M) = 0x00 – (M)
M ← – (M) = 0x00 – (M)
M ← – (M) = 0x00 – (M)
A ← – (A) = 0x00 – (A)
X ← – (X) = 0x00 – (X)
C
A ← (A[3:0]:A[7:4])
destination
Uses 1 Bus Cycle
b7
b7
X:A ← (X) × (A)
Description
A ← (A) | (M)
b7
X ← (M)
Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2)
← (M)
b0
b0
source
b0
C
0
0 – –
0 – –
– 0 – – – 0
– – – – – –
– – – – – –
0 – –
– – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
V H I N Z C
– –
– – 0
– –
– –
on CCR
Effect
–
–
–
– INH
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
DIR/DIR
DIR/IX+
IMM/DIR
IX+/DIR
INH
DIR
INH
INH
IX1
IX
SP1
INH
INH
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
INH
INH
INH
INH
INH
DIR
INH
INH
IX1
IX
SP1
9EDE
9EDA
9EEE
9EEA
9E68
9E64
9E60
9E69
AE
BE
CE
DE
EE
AA
BA
CA
DA
EA
FE
9D
FA
4E
5E
6E
7E
8B
8A
38
48
58
68
78
34
44
54
64
74
42
30
40
50
60
70
62
87
89
86
88
39
49
59
69
79
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd
ff
ff
dd
ff
ff
dd dd
dd
ii dd
dd
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd
ff
ff
2
3
4
4
3
3
5
4
5
1
1
5
4
6
5
1
1
5
4
6
5
5
4
5
5
5
1
1
5
4
6
1
1
2
3
4
4
3
3
5
4
2
2
2
3
3
3
5
1
1
5
4
6
101
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