R5F21238JFP#U0 Renesas Electronics America, R5F21238JFP#U0 Datasheet - Page 358
![IC R8C/23 MCU FLASH 64K 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F21238JFP#U0
Manufacturer Part Number
R5F21238JFP#U0
Description
IC R8C/23 MCU FLASH 64K 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21238JFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21238JFP#U0R5F21238JFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21238JFP#U0R5F21238JFP#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 358 of 551
- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.33
Figure 16.34
(slave output)
ICSR register
ICSR register
(master output)
(master output)
ICDRS register
ICDRT register
(master output)
(master output)
(slave output)
ICSR register
ICSR register
TDRE bit in
TEND bit in
ICDRS register
ICDRT register
TDRE bit in
TEND bit in
by program
Processing
by program
Processing
SDA
SDA
SDA
SCL
SDA
SCL
Operating Timing in Master Transmit Mode (I
Operating Timing in Master Transmit Mode (I
1
0
1
0
1
0
1
0
(2) Instruction of
(3) Data write to ICDRT
start condition
generation
register
Page 336 of 501
9
A
b7
1
b7
1
b6
(3) Data write to ICDRT
2
register (1st byte)
b6
2
b5
3
b5
Slave address
3
Address + R/W
b4
4
b4
Address + R/W
4
Data n
b3
5
Data n
b3
5
b2
(4) Data write to ICDRT
6
register (2nd byte)
b2
6
b1
7
2
2
C Bus Interface Mode) (1)
C Bus Interface Mode) (2)
b1
7
b0
R/W
8
(6) Generate stop condition and
16. Clock Synchronous Serial Interface
set TEND bit to 0
b0
8
A
9
A/A
9
(7) Set to slave receive mode
(5) Data write to ICDRT
register (3rd byte)
Data 1
Data 1
b7
1
Data 2
b6
2
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