R5F21238JFP#U0 Renesas Electronics America, R5F21238JFP#U0 Datasheet - Page 61
![IC R8C/23 MCU FLASH 64K 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F21238JFP#U0
Manufacturer Part Number
R5F21238JFP#U0
Description
IC R8C/23 MCU FLASH 64K 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21238JFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21238JFP#U0R5F21238JFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21238JFP#U0R5F21238JFP#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 6.5
Voltage Monitor 1 Circuit Control Register
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VW1C register.
The value other than the VW1CO and VW1C6 bits remains unchanged after softw are reset, w atchdog timer reset,
and voltage monitor 2 reset.
The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit
enabled). Set the VW1C0 bit to 0 (disable), w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).
The VW1C7 bit is enabled w hen the VW1C1 bit is set to 1 (digital filter disabled mode).
b3 b2
0
VW1C Register
b1 b0
Bit Symbol
VW1C0
VW1C2
VW1C6
VW1C7
VW1C1
VW1F0
VW1F1
Symbol
VW1C
Page 39 of 501
(b3)
—
Voltage monitor 1 reset enable
bit
Voltage monitor 1 digital filter
disable mode select bit
Reserved bit
Reserved bit
Sampling clock select bits
Voltage monitor 1 circuit mode
select bit
Voltage monitor 1 reset generation
condition select bit
(3)
(1)
Address
Bit Name
0036h
(4)
b5 b4
0 0 : fOCO-S divide-by-1
0 1 : fOCO-S divide-by-2
1 0 : fOCO-S divide-by-4
1 1 : fOCO-S divide-by-8
The LVD1ON bit in the OFS register is set to 1: 0000X000b
Power-on reset, v oltage monitor 1 reset or the LVD1ON bit
in the OFS register is set to 0: 0100X001b
0 : Disable
1 : Enable
0 : Digital filter enabled mode
1 : Digital filter disabled mode
Set to 0
When read, the content is undefined.
When the VW1C0 bit is set to 1 (enables
voltage monitor 1 reset), set to 1.
When the VW1C1 bit is set to 1 (digital filter
disabled mode), set to 1.
(digital filter circuit enabled)
(digital filter circuit disabled)
Function
After Reset
6. Voltage Detection Circuit
(2)
RW
RW
RW
RW
RW
RW
RW
RW
RO
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