C8051F531-IT Silicon Laboratories Inc, C8051F531-IT Datasheet - Page 89
![IC 8051 MCU 8K FLASH 20TSSOP](/photos/12/46/124608/silicon_laboratories_inc-20-tssop_sml.jpg)
C8051F531-IT
Manufacturer Part Number
C8051F531-IT
Description
IC 8051 MCU 8K FLASH 20TSSOP
Manufacturer
Silicon Laboratories Inc
Series
C8051F53xr
Specifications of C8051F531-IT
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.25 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-TSSOP
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
336-1393
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F531-IT
Manufacturer:
SILICON
Quantity:
205
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SFR Definition 8.5. ACC: Accumulator
SFR Definition 8.6. B: B Register
8.3. Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the peripherals and internal clocks active. In Stop mode, the CPU is halted, all
interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped
(analog peripherals remain in their selected states; the external oscillator is not affected). Since clocks are
running in Idle mode, power consumption is dependent upon the system clock frequency and the number
of peripherals left in active mode before entering Idle. Stop mode consumes the least power. SFR Defini-
tion 8.7 describes the Power Control Register (PCON) used to control the CIP-51's power management
modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power
management of the entire MCU is better accomplished by enabling/disabling individual peripherals as
needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital
peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off the oscil-
lators lowers power consumption considerably; however a reset is required to restart the MCU.
The C8051F52x/F52xA/F53x/F53xAdevices feature a low-power SUSPEND mode, which stops the inter-
nal oscillator until a wakening event occurs. See Section “14.1.1. Internal Oscillator Suspend Mode” on
page 135 for more information.
Bits7–0: ACC: Accumulator.
Bits7–0: B: B Register.
ACC.7
R/W
R/W
B.7
Bit7
Bit7
This register is the accumulator for arithmetic operations.
This register serves as a second accumulator for certain arithmetic operations.
ACC.6
R/W
R/W
B.6
Bit6
Bit6
ACC.5
R/W
R/W
B.5
Bit5
Bit5
ACC.4
C8051F52x/F52xA/F53x/F53xA
R/W
R/W
B.4
Bit4
Bit4
Rev. 1.3
ACC.3
R/W
R/W
B.3
Bit3
Bit3
ACC.2
R/W
R/W
Bit2
B.2
Bit2
ACC.1
R/W
R/W
B.1
Bit1
Bit1
SFR Address: 0xE0
SFR Address: 0xF0
ACC.0
R/W
R/W
B.0
Bit0
Bit0
00000000
Addressable
Reset Value
00000000
Addressable
Reset Value
Bit
Bit
89
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