MC68711E20CFNE3 Freescale Semiconductor, MC68711E20CFNE3 Datasheet - Page 95

• Manufacturer Part Number: MC68711E20CFNE3
• Description: IC MCU 8BIT 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68711E20CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: M687xx
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4.6 Timer Control 1 Register
The bits of the timer control 1 register (TCTL1) specify the action taken as a result of a successful OCx
compare.
OM2–OM5 — Output Mode Bits
OL2–OL5 — Output Level Bits
8.4.7 Timer Interrupt Mask 1 Register
The timer interrupt mask 1 register (TMSK1) is an 8-bit register used to enable or inhibit the timer input
capture and output compare interrupts.
OC1I–OC4I — Output Compare x Interrupt Enable Bits
I4/O5I — Input Capture 4 or Output Compare 5 Interrupt Enable Bit
IC1I–IC3I — Input Capture x Interrupt Enable Bits
Freescale Semiconductor
These control bit pairs are encoded to specify the action taken after a successful OCx compare. OC5
functions only if the I4/O5 bit in the PACTL register is clear. Refer to
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested.
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit. When I4/O5 in PACTL
is 0, I4/O5I is the output compare 5 interrupt enable bit.
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested.
Address:
Address:
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1
enable the corresponding interrupt sources.
Reset:
Reset:
Read:
Read:
Write:
Write:
$0020
$0022
OC1I
OM2
Bit 7
Bit 7
Figure 8-12. Timer Interrupt Mask 1 Register (TMSK1)
OMx
0
0
0
0
1
1
Figure 8-11. Timer Control 1 Register (TCTL1)
Table 8-3. Timer Output Compare Actions
OLx
OC2I
OL2
0
1
0
1
6
0
6
0
MC68HC711D3 Data Sheet, Rev. 2.1
Timer disconnected from output pin logic
Toggle OCx output line
Clear OCx output line to 0
Set OCx output line to 1
OC3I
OM3
5
0
5
0
Action Taken on Successful Compare
NOTE
OC4I
OL3
4
0
4
0
I4/O5I
OM4
3
0
3
0
OL4
IC1I
2
0
2
0
Table 8-3
OM5
IC2I
1
0
1
0
for the coding.
Output Compare (OC)
Bit 0
Bit 0
OL5
IC3I
0
0
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