MC68711E20CFNE3 Freescale Semiconductor, MC68711E20CFNE3 Datasheet - Page 99

• Manufacturer Part Number: MC68711E20CFNE3
• Description: IC MCU 8BIT 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68711E20CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: M687xx
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PR1 and PR0 — Timer Prescaler Select Bits
8.5.2 Timer Interrupt Flag 2 Register
Bits of the timer interrupt flag 2 register (TFLG2) indicate the occurrence of timer system events. Coupled
with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either
a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position.
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
RTIF — Real-Time Interrupt Flag
PAOVF — Pulse Accumulator Overflow Interrupt Flag
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Bits 3–0 — Not implemented
8.5.3 Pulse Accumulator Control Register
Bits RTR1 and RTR0 of the pulse accumulator control register (PACTL) select the rate for the real-time
interrupt system. Bit DDRA3 determines whether port A bit three is an input or an output when used for
general-purpose I/O. The remaining bits control the pulse accumulator.
Freescale Semiconductor
Refer to
Set when TCNT changes from $FFFF to $0000
The RTIF status bit is automatically set to 1 at the end of every RTI period. To clear RTIF, write a byte
to TFLG2 with bit 6 set.
Refer to
Refer to
Always read 0.
Table
8.7 Pulse
8.7 Pulse
Address:
Address:
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2
enable the corresponding interrupt sources.
Reset:
Reset:
Read:
Read:
Write:
Write:
8-4.
Figure 8-18. Pulse Accumulator Control Register (PACTL)
Accumulator.
Accumulator.
DDRA7
$0025
$0026
Bit 7
TOF
Bit 7
0
Figure 8-17. Timer Interrupt Flag 2 Register (TFLG2)
0
PAEN
RTIF
6
0
6
0
MC68HC711D3 Data Sheet, Rev. 2.1
PAMOD
PAOVF
5
0
5
0
PEDGE
NOTE
PAIF
4
0
4
0
DDRA3
3
0
0
3
0
I4/O5
2
0
0
2
0
RTR1
1
0
0
1
0
RTR0
Bit 0
Bit 0
0
0
0
Real-Time Interrupt
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