SAK-XC866-4FRI BC Infineon Technologies, SAK-XC866-4FRI BC Datasheet - Page 68
![IC MCU 8BIT 16KB FLSH TSSOP-38-1](/photos/12/46/124655/sak-xc866-4fri_bc_sml.jpg)
SAK-XC866-4FRI BC
Manufacturer Part Number
SAK-XC866-4FRI BC
Description
IC MCU 8BIT 16KB FLSH TSSOP-38-1
Manufacturer
Infineon Technologies
Series
XC8xxr
Datasheet
1.SAF-XC866-2FRI_BC.pdf
(116 pages)
Specifications of SAK-XC866-4FRI BC
Core Processor
XC800
Core Size
8-Bit
Speed
86MHz
Connectivity
SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
38-TSSOP
For Use With
MCBXC866 - BOARD EVAL FOR INFINEON XC86X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
SAK-XC866-4FRIBC
SAK-XC866-4FRIBCINTR
SAK-XC866-4FRIBCTR
SAK-XC866-4FRIBCTR
SAKXC8664FRIBCXT
SP000210680
SAK-XC866-4FRIBCINTR
SAK-XC866-4FRIBCTR
SAK-XC866-4FRIBCTR
SAKXC8664FRIBCXT
SP000210680
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3.10
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failures. The WDT is reset at a regular interval that is
predefined by the user. The CPU must service the WDT within this interval to prevent the
WDT from causing an XC866 system reset. Hence, routine service of the WDT confirms
that the system is functioning properly. This ensures that an accidental malfunction of
the XC866 will be aborted in a user-specified time period. In debug mode, the WDT is
suspended and stops counting. Therefore, there is no need to refresh the WDT during
debugging.
Features:
• 16-bit Watchdog Timer
• Programmable reload value for upper 8 bits of timer
• Programmable window boundary
• Selectable input frequency of f
• Time-out detection with NMI generation and reset prewarning activation (after which
The WDT is a 16-bit timer incremented by a count rate of f
16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT
can be preset to a user-programmable value via a watchdog service access in order to
modify the watchdog expire time period. The lower 8 bits are reset on each service
access.
Figure 27
Data Sheet
ENWDT
ENWDT_P
a system reset will be performed)
Figure 27
f
PCLK
Watchdog Timer
Logic
WDT Block Diagram
shows the block diagram of the WDT unit.
1:128
1:2
PCLK
/2 or f
WDTIN
MUX
64
PCLK
/128
WDT Low Byte
Control
WDT
Overflow/Time-out Control &
Window-boundary control
Clear
PCLK
Functional Description
WDT High Byte
WDTWINB
/2 or f
WDTREL
PCLK
V1.2, 2007-10
/128. This
XC866
WDTTO
WDTRST
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