SAK-XC866-4FRI BC Infineon Technologies, SAK-XC866-4FRI BC Datasheet - Page 87
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SAK-XC866-4FRI BC
Manufacturer Part Number
SAK-XC866-4FRI BC
Description
IC MCU 8BIT 16KB FLSH TSSOP-38-1
Manufacturer
Infineon Technologies
Series
XC8xxr
Datasheet
1.SAF-XC866-2FRI_BC.pdf
(116 pages)
Specifications of SAK-XC866-4FRI BC
Core Processor
XC800
Core Size
8-Bit
Speed
86MHz
Connectivity
SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
38-TSSOP
For Use With
MCBXC866 - BOARD EVAL FOR INFINEON XC86X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
SAK-XC866-4FRIBC
SAK-XC866-4FRIBCINTR
SAK-XC866-4FRIBCTR
SAK-XC866-4FRIBCTR
SAKXC8664FRIBCXT
SP000210680
SAK-XC866-4FRIBCINTR
SAK-XC866-4FRIBCTR
SAK-XC866-4FRIBCTR
SAKXC8664FRIBCXT
SP000210680
3.19
The On-Chip Debug Support (OCDS) provides the basic functionality required for the
software development and debugging of XC800-based systems.
The OCDS design is based on these principles:
• use the built-in debug functionality of the XC800 Core
• add a minimum of hardware overhead
• provide support for most of the operations by a Monitor Program
• use standard interfaces to communicate with the Host (a Debugger)
Features:
• Set breakpoints on instruction address and within a specified address range
• Set breakpoints on internal RAM address
• Support unlimited software breakpoints in Flash/RAM code region
• Process external breaks
• Step through the program code
The OCDS functional blocks are shown in
block at the center of OCDS system brings together control signals and supports the
overall functionality. The MMC communicates with the XC800 Core, primarily via the
Debug Interface, and also receives reset and clock signals. After processing memory
address and control signals from the core, the MMC provides proper access to the
dedicated extra-memories: a Monitor ROM (holding the code) and a Monitor RAM (for
work-data and Monitor-stack). The OCDS system is accessed through the JTAG
which is an interface dedicated exclusively for testing and debugging activities and is not
normally used in an application. The dedicated MBC pin is used for external
configuration and debugging control.
Note: All the debug functionality described here can normally be used only after XC866
1)
Data Sheet
The pins of the JTAG port can be assigned to either Port 0 (primary) or Ports 1 and 2 (secondary).
User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.
has been started in OCDS mode.
On-Chip Debug Support
Figure
83
35. The Monitor Mode Control (MMC)
Functional Description
V1.2, 2007-10
XC866
1)
,