SAK-C161JC-LF CA Infineon Technologies, SAK-C161JC-LF CA Datasheet - Page 36

• Manufacturer Part Number: SAK-C161JC-LF CA
• Description: IC MCU 16BIT 256KB TQFP-128-2
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C161JC-LF CA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SLDM, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 93
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 128-LFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: SAKC161JCLFCA; SP000057699

Serial Data Link Module (SDLM)
The Serial Data Link Module (SDLM) provides serial communication via a J1850 type
multiplexed serial bus via an external J1850 bus transceiver. The module conforms to
the SAE Class B J1850 specification for variable pulse width modulation (VPW). The
SDLM is integrated as an on-chip peripheral and is connected to the CPU via the XBUS.
General SDLM Features:
• Compliant to the SAE Class B J1850 specification (VPW)
• Class 2 protocol fully supported
• Variable Pulse Width (VPW) operation at 10.4 kBaud
• High Speed 4X operation at 41.6 kBaud
• Programmable Normalization Bit
• Programmable Delay for transceiver interface
• Digital Noise Filter
• Power Down mode with automatic wakeup support upon bus activity
• Single Byte Header and Consolidated Header supported
• CRC generation and checking
• Receive and transmit Block Mode
Data Link Operation Features:
• 11 Byte Transmit Buffer
• Double buffered 11 Byte receive buffer (optional overwrite enable)
• Support for In Frame Response (IFR) types 1, 2 and 3
• Transmit and Receiver Message Buffers configurable for either FIFO or Byte mode
• Advanced Interrupt Handling with 8 separately enabled sources:
• Automatic IFR transmission (Types 1 and 2) for 3-Byte consolidated headers
• User configurable clock divider
• Bus status flags (IDLE, EOF, EOD, SOF, Tx and Rx in progress)
Note: When the SDLM is used with the interface lines assigned to Port 4, the interface
Data Sheet
Error, format or bus shorted
CRC error
Lost Arbitration
Break received
In-Frame-Response request
Header received
Complete message received
Transmit successful
lines override the segment address lines and the segment address output on
Port 4 is therefore limited to 6/4 bits i.e. address lines A21/A19 … A16. CS lines
can be used to increase the total amount of addressable external memory.
32
C161CS/JC/JI-32R
C161CS/JC/JI-L
V3.0, 2001-01