CY8C3866PVI-070 Cypress Semiconductor Corp, CY8C3866PVI-070 Datasheet - Page 16
![IC MCU 8BIT 64KB FLASH 48SSOP](/photos/39/70/397035/cy8c_sml.jpg)
CY8C3866PVI-070
Manufacturer Part Number
CY8C3866PVI-070
Description
IC MCU 8BIT 64KB FLASH 48SSOP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ 3 CY8C38xxr
Specifications of CY8C3866PVI-070
Package / Case
*
Voltage - Supply (vcc/vdd)
1.71 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
67MHz
Number Of I /o
25
Eeprom Size
2K x 8
Core Processor
8051
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 2x20b, D/A 4x8b
Oscillator Type
Internal
Peripherals
CapSense, DMA, LCD, POR, PWM, WDT
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, UART/USART
Core Size
8-Bit
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Technology
CMOS
Processing Unit
Microcontroller
Operating Supply Voltage (min)
1.8V
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Package Type
SSOP
Screening Level
Industrial
Pin Count
48
Mounting
Surface Mount
Rad Hardened
No
Processor Series
CY8C38
Core
8051
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART, USB
Maximum Clock Frequency
67 MHz
Number Of Programmable I/os
28 to 72
Number Of Timers
4
Operating Supply Voltage
0.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Controller Family/series
(8051) PSOC 3
No. Of I/o's
25
Eeprom Memory Size
2KB
Ram Memory Size
8KB
Cpu Speed
67MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY8C3866PVI-070
Manufacturer:
CYPRESS厂技术支持
Quantity:
20 000
4.4.2 DMA Features
4.4.3 Priority Levels
The CPU always has higher priority than the DMA controller
when their accesses require the same bus resources. Due to the
system architecture, the CPU can never starve the DMA. DMA
channels of higher priority (lower priority number) may interrupt
current DMA transfers. In the case of an interrupt, the current
transfer is allowed to complete its current transaction. To ensure
latency limits when multiple DMA accesses are requested
simultaneously, a fairness algorithm guarantees an interleaved
minimum percentage of bus bandwidth for priority levels 2
through 7. Priority levels 0 and 1 do not take part in the fairness
algorithm and may use 100 percent of the bus bandwidth. If a tie
occurs on two DMA requests of the same priority level, a simple
round robin method is used to evenly share the allocated
bandwidth. The round robin allocation can be disabled for each
DMA channel, allowing it to always be at the head of the line.
Document Number: 001-11729 Rev. *R
24 DMA channels
Each channel has one or more transaction descriptors (TD) to
configure channel behavior. Up to 128 total TDs can be defined
TDs can be dynamically updated
Eight levels of priority per channel
Any digitally routable signal, the CPU, or another DMA channel,
can trigger a transaction
Each channel can generate up to two interrupts per transfer
Transactions can be stalled or canceled
Supports transaction size of infinite or 1 to 64 KB
TDs may be nested and/or chained for complex transactions
ADDR 16/32
READY
WRITE
DATA
CLK
ADDRESS Phase
Basic DMA Read Transfer without wait states
A
DATA Phase
B
Figure 4-1. DMA Timing Diagram
DATA (A)
ADDR 16/32
Priority levels 2 to 7 are guaranteed the minimum bus bandwidth
shown in
1 have satisfied their requirements.
Table 4-7. Priority Levels
When the fairness algorithm is disabled, DMA access is granted
based solely on the priority level; no bus bandwidth guarantees
are made.
4.4.4 Transaction Modes Supported
The flexible configuration of each DMA channel and the ability to
chain multiple channels allow the creation of both simple and
complex use cases. General use cases include, but are not
limited to:
4.4.4.1 Simple DMA
In a simple DMA case, a single TD transfers data between a
source and sink (peripherals or memory location). The basic
timing diagrams of DMA read and write cycles are shown in
Figure
to the Technical Reference Manual.
READY
WRITE
DATA
Priority Level
CLK
4-1. For more description on other transfer modes, refer
Table 4-7
0
1
2
3
4
5
6
7
ADDRESS Phase
after the CPU and DMA priority levels 0 and
PSoC
Basic DMA Write Transfer without wait states
A
% Bus Bandwidth
®
3: CY8C38 Family
100.0
100.0
50.0
25.0
12.5
6.2
3.1
1.5
DATA Phase
DATA (A)
Data Sheet
B
Page 16 of 129
[+] Feedback