MC9328MX21SCVK Freescale Semiconductor, MC9328MX21SCVK Datasheet - Page 18

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MC9328MX21SCVK

Manufacturer Part Number
MC9328MX21SCVK
Description
IC MCU I.MX21 266MHZ 289-MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX21r
Datasheets

Specifications of MC9328MX21SCVK

Core Processor
ARM9
Core Size
32-Bit
Speed
266MHz
Connectivity
1-Wire, EBI/EMI, I²C, IrDA, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
192
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
1.45 V ~ 3.3 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-MAPBGA
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9328MX21SCVK
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9328MX21SCVKR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Specifications
3.6
The timing relationships of the Reset module with the POR and RESET_IN are shown in
Figure
QVDD is powered up to prevent forward biasing.
18
MF integer part
MF numerator
MF denominator
Frequency lock-in time after
full reset
Frequency lock-in time after
partial reset
Phase lock-in time after
full reset
Phase lock-in time after
partial reset
Frequency jitter (p-p)
Phase jitter (p-p)
Power dissipation
RESET_DRAM
3. Be aware that NVDD must ramp up to at least 1.7V for NVDD1 and 2.7V for NVDD2-6 before
RESET_POR
RESET_OUT
Reset Module
Parameter
HRESET
CLK32
HCLK
POR
Can be adjusted depending on the crystal
start-up time 32kHz or 32.768kHz
Should be less than the denominator
FOL mode for non-integer MF
(does not include pre-multi lock-in time)
FOL mode for non-integer MF
(does not include pre-multi lock-in time)
FPL mode and integer MF
(does not include pre-multi lock-in time)
FPL mode and integer MF
(does not include pre-multi lock-in time)
Integer MF, FPL mode, Vcc=1.7V
FOL mode, integer MF,
f
Table 11. DPLL Specifications (Continued)
dck
Figure 2. Timing Relationship with POR
= 560 MHz, Vcc = 1.5V
MC9328MX21 Technical Data, Rev. 3.4
1
Test Conditions
Exact 300ms
2
Minimum
3
350
220
480
360
5
0
1
4
7 cycles @ CLK32
Typical
0.02
400
280
530
410
1.0
1.5
14 cycles @ CLK32
Freescale Semiconductor
Maximum
Figure 2
1022
1023
0.03
450
330
580
460
1.5
15
and
2•T
(Avg)
Unit
mW
T
T
T
T
ns
ref
ref
ref
ref
dck

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