MCF5282CVM66 Freescale Semiconductor, MCF5282CVM66 Datasheet - Page 623
MCF5282CVM66
Manufacturer Part Number
MCF5282CVM66
Description
IC MPU 512K 66MHZ 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVM66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Controller Family/series
ColdFire
No. Of I/o's
150
Ram Memory Size
64KB
Cpu Speed
66.67MHz
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of Pwm Channels
8
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Debug Support
target instruction. The PST can continue with the next instruction before the address has completely
displayed on DDATA because of the DDATA FIFO. If the FIFO is full and the next instruction has captured
values to display on DDATA, the pipeline stalls (PST = 0x0) until space is available in the FIFO.
30.4
Programming Model
In addition to the existing BDM commands that provide access to the processor’s registers and the memory
subsystem, the debug module contains 19 registers to support the required functionality. These registers
are also accessible from the processor’s supervisor programming model by executing the WDEBUG
instruction (write only). Thus, the breakpoint hardware in the debug module can be written by the external
development system using the debug serial interface or by the operating system running on the processor
core. Software is responsible for guaranteeing that accesses to these resources are serialized and logically
consistent. Hardware provides a locking mechanism in the CSR to allow the external development system
to disable any attempted writes by the processor to the breakpoint registers (setting CSR[IPW]). BDM
commands must not be issued if the device is using the WDEBUG instruction to access debug module
registers or the resulting behavior is undefined.
These registers, shown in
Figure
30-4, are treated as 32-bit quantities, regardless of the number of
implemented bits.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor
30-5
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