MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 511

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PORTn bits are described in
26.3.2.2 Port Data Direction Registers (DDRn)
The DDRs control the direction of the port n pin drivers when the pins are configured for digital I/O.
Most DDRs have a full 8-bit implementation, as shown in
than eight bits. Their bit definitions are shown in
The DDRs are read/write. At reset, all bits in the DDRs are cleared.
Setting any bit in a DDRn register configures the corresponding port n pin as an output. Clearing any bit
in a DDRn register configures the corresponding pin as an input.
Freescale Semiconductor
Address
Address
Reset
Reset
R/W:
Register
R/W:
Field
Field
8-bit
7-bit
6-bit
4-bit
7-bit
6-bit
4-bit
DDRn7
IPSBAR + 0x10_0014 (DDRA), 0x10_0015 (DDRB), 0x10_0016 (DDRC), 0x10_0017 (DDRD),
7
7
0x10_001C (DDRJ), 0x10_001D (DDRDD), 0x10_001E (DDREH), 0x10_001F (DDREL)
Table 26-3. PORTn (8-bit, 7-bit, 6-bit, and 4-bit) Field Descriptions
0x10_0018 (DDRE), 0x10_0019 (DDRF), 0x10_001A (DDRG), 0x10_001B (DDRH),
IPSBAR + 0x10_000F (PORTTC), 0x10_0010 (PORTTD), 0x10_0011 (PORTUA)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
DDRn6
Bits
7–0
6–0
5–0
3–0
7–6
7–4
Table
7
Figure 26-7. Port Data Direction Registers (8-bit)
Figure 26-6. Port Output Data Registers (4-bit)
6
—
26-3.
R
DDRn5
5
PORTnx
Name
—
DDRn4
Figure
4
4
0000_1111
0000_0000
Port output data bits.
1 Drives 1 when the port n pin is a digital output
0 Drives 0 when the port n pin is a digital output
Reserved, should be cleared.
R/W
26-8,
PORTn3
DDRn3
Figure
3
3
Figure
26-7. The remaining DDRs use fewer
PORTn2
DDRn2
26-9, and
Description
2
2
R/W
PORTn1
DDRn1
Figure
1
1
General Purpose I/O Module
26-10.
PORTn0
DDRn0
0
0
26-11