MCF5282CVF80 Freescale Semiconductor, MCF5282CVF80 Datasheet - Page 140

• Manufacturer Part Number: MCF5282CVF80
• Description: IC MPU 32BIT 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF528x
• Maximum Speed: 80 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 150
• Interface Type: CAN/Ethernet/I2C/QSPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 12
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Power Management
7.2.3.2
The LPCR controls chip operation and module operation during low-power modes.
7-4
Bits
7–6
4–3
5
2
1
0
Low-Power Control Register (LPCR)
Address
Reset
Field
R/W
STPMD
LVDSE
Name
LPMD
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
—
—
—
Figure 7-2. Low-Power Control Register (LPCR)
7
LPMD
Low-power mode select. Used to select the low-power mode the chip
enters once the ColdFire CPU executes the STOP instruction. These bits
must be written prior to instruction execution for them to take effect. The
LPMD[1:0] bits are readable and writable in all modes.
the four different power modes that can be configured with the LPMD bit
field.
Reserved, should be cleared.
PLL/CLKOUT stop mode. Controls PLL and CLKOUT operation in stop
mode as shown in
Reserved, should be cleared.
LDV standby enable. Controls whether the PMM enters VREG Standby
Mode (LVD disabled) or VREG Pseudo-Standby (LVD enabled) mode when
the PMM receives a power down request. This bit has no effect if the
RCR[LVDE] bit is a logic 0.
1 VREG Pseudo-Standby mode (LVD enabled on power down request).
0 VREG Standby mode (LVD disabled on power down request).
Reserved, should be cleared.
Table 7-4. LPCR Field Descriptions
Table 7-5. Low-Power Modes
6
LPMD[1:0]
11
10
01
00
—
5
IPSBAR + 0x0011_0007
Table 7-6
0000_0010
4
STPMD
R/W
Description
3
DOZE
Mode
STOP
WAIT
RUN
—
2
LVDSE
1
Table 7-5
—
Freescale Semiconductor
0
illustrates