MCF5282CVF80 Freescale Semiconductor, MCF5282CVF80 Datasheet - Page 625

• Manufacturer Part Number: MCF5282CVF80
• Description: IC MPU 32BIT 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF528x
• Maximum Speed: 80 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 150
• Interface Type: CAN/Ethernet/I2C/QSPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 12
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

30.4.1
In the Revision A implementation of the debug module, certain hardware structures are shared between
BDM and breakpoint functionality as shown in
Thus, loading a register to perform a specific function that shares hardware resources is destructive to the
shared function. For example, a BDM command to access memory overwrites an address breakpoint in
ABHR. A BDM write command overwrites the data breakpoint in DBR.
30.4.2
The AATR, shown in
register value is compared with address attribute signals from the processor’s local high-speed bus, as
defined by the setting of the trigger definition register (TDR).
Freescale Semiconductor
0x0A–0x0B Reserved
0x01–0x05 Reserved
DRc[4–0]
0x0C
0x0D
0x0E
Revision A Shared Debug Resources
Address Attribute Trigger Register (AATR)
0x00
0x06
0x07
0x08
0x09
0x0F
Register
Debug control registers can be written by the external development system
or the CPU through the WDEBUG instruction.
CSR is write-only from the programming model. It can be read or written
through the BDM port using the
ABHR
AATR
DBR
Configuration/status register
Address attribute trigger register
Trigger definition register
Program counter breakpoint register
Program counter breakpoint mask register
Address breakpoint high register
Address breakpoint low register
Data breakpoint register
Data breakpoint mask register
Figure
Bus attributes for all memory commands
Address for all memory commands
Data for all BDM write commands
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 30-4. Rev. A Shared BDM/Breakpoint Hardware
30-5, defines address attributes and a mask to be matched in the trigger. The
Register Name
Table 30-3. BDM/Breakpoint Registers
BDM Function
RDMREG
Table
NOTE
30-4.
and
Abbreviation
WDMREG
Attributes for address breakpoint
Address for address breakpoint
Data for data breakpoint
DBMR
PBMR
ABHR
AATR
ABLR
CSR
TDR
PBR
DBR
—
—
Breakpoint Function
commands.
0x00010_0000
0x0000_0005
0x0000_0000
Initial State
—
—
—
—
—
—
—
—
p. 30-10
p. 30-14
p. 30-13
p. 30-13
p. 30-12
p. 30-12
p. 30-7
p. 30-9
p. 30-9
Page
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Debug Support
30-7