MCF5282CVF80 Freescale Semiconductor, MCF5282CVF80 Datasheet - Page 398

• Manufacturer Part Number: MCF5282CVF80
• Description: IC MPU 32BIT 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF528x
• Maximum Speed: 80 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 150
• Interface Type: CAN/Ethernet/I2C/QSPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 12
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

DMA Timers (DTIM0–DTIM3)
21-6
Field
CAP
REF
7–2
1
0
IPSBAR
Offset:
Reset:
Reserved, must be cleared.
Output reference event. The counter value (DTCNn) equals DTRRn. Writing a 1 to REF clears the event condition.
Writing a 0 has no effect.
Capture event. The counter value has been latched into DTCRn. Writing a 1 to CAP clears the event condition.
Writing a 0 has no effect.
W
R
0x00_0403 (DTER0)
0x00_0443 (DTER1)
0x00_0483 (DTER2)
0x00_04C3 (DTER3)
0
0
7
CAP
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
0
1
1
1
1
1
1
1
1
REF
6
0
0
0
1
1
1
1
DTMRn[CE]
Table 21-4. DTERn Field Descriptions
XX
00
00
01
01
10
10
11
11
DTMRn[ORRI]
Figure 21-4. DTERn Registers
0
0
5
X
0
0
1
1
[DMAEN]
DTXMRn
X
0
1
0
1
0
1
0
1
DTXMRn[DMAEN]
0
0
4
Description
Capture on falling edge and trigger interrupt
Capture on rising edge and trigger interrupt
Capture on any edge and trigger interrupt
Capture on falling edge and trigger DMA
Capture on rising edge and trigger DMA
Capture on any edge and trigger DMA
X
0
1
0
1
Disable capture event output
Disable capture event output
0
0
3
Interrupt request asserted
No event
DMA request asserted
No request asserted
No request asserted
0
0
2
No event
Access: User read/write
REF
w1c
Freescale Semiconductor
0
1
CAP
w1c
0
0