ST16C552CJ68-F Exar Corporation, ST16C552CJ68-F Datasheet
ST16C552CJ68-F
Specifications of ST16C552CJ68-F
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ST16C552CJ68-F Summary of contents
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... 70° C PLCC -40° 85° C PLCC -40° 85° C ST16C552 ST16C552A PARALLEL PRINTER PORT December 2003 PLCC Package 60 INTB 59 INTP 58 -SLCTIN 57 INIT 56 -AUTOFDXT 55 -STROBE 54 GND 53 PD0 ST16C552CJ68 52 PD1 ST16C552ACJ68 51 PD2 50 PD3 49 PD4 48 PD5 47 PD6 46 PD7 45 INTA 44 RDOUT Device Status Active Active Active Active ...
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ST16C552/552A Figure 1, Block Diagram D0-D7 -IOR -IOW -RESET BIDEN A0-A2 -CSA -CSB -CSP INT A,B INTP -RXRDY -TXRDY Rev. 3.40 Transmit Transmit FIFO Shift Registers Register Receive Receive FIFO Shift Registers Register Printer Data Ports Printer Control Logic Modem ...
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SYMBOL DESCRIPTION Symbol Pin -ACK 68 -AutoFDXT 56 BIDEN 1 BUSY 66 CLK 4 -CSA 32 -CSB 3 -CSP 38 D0-D7 14-21 Rev. 3.40 Signal Type I Address-0 Select Bit - Internal registers address ...
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ST16C552/552A SYMBOL DESCRIPTION Symbol Pin -ERROR 63 GND 2,7,54 27 INIT 57 INT A/B 45,60 -INTP 59 INTSEL 43 Rev. 3.40 Signal Type I Error, Printer (with internal pull-up) - General purpose input or line printer error. This pin may ...
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SYMBOL DESCRIPTION Symbol Pin -IOR 37 -IOW 36 PD7-PD0 46- RDOUT 44 -RESET 39 -RXRDY A/B 9,61 Rev. 3.40 Signal Type trailing edge of -IOR (end of the external CPU read cycle). I Read strobe.- A logic 0 ...
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ST16C552/552A SYMBOL DESCRIPTION Symbol Pin SLCT 65 -SLCTIN 58 -STROBE 55 -TXRDY A/B 22,42 VCC 23,40,64 -CD A/B 29,8 -CTS A/B 28,13 Rev. 3.40 Signal Type reached. I Select (with internal pull-up) - General purpose input or line printer select ...
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SYMBOL DESCRIPTION Symbol Pin -DSR A/B 31,5 -DTR A/B 25,11 -RI A/B 30,6 -RTS A/B 24,12 RX A/B 41,62 Rev. 3.40 Signal Type effect on the transmit or receive operation. I Data Set Ready (active low) - These inputs are ...
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ST16C552/552A Symbol Pin TX A/B 26,10 GENERAL DESCRIPTION The 552/552A provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to- parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into ...
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The rich feature set of the 552/552A is available through internal registers. Selectable receive FIFO trigger levels, selectable TX and RX baud rates, modem interface controls, and a power-down mode are all standard features. Following a power on reset or ...
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ST16C552/552A Table 4, INTERNAL REGISTER DECODE READ MODE General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): Note Receive Holding Register Interrupt Status Register ...
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FIFO Operation The 16 byte transmit and receive data FIFO’s are enabled by the FIFO Control Register (FCR) bit-0. The user can set the receive trigger level via FCR bits 6/ 7 but not the transmit trigger level. The transmit ...
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ST16C552/552A same system design. The rate table is configured via the DLL and DLM internal register functions. Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator. Programming ...
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DMA Operation The 552/552A FIFO trigger level provides additional flexibility to the user for block mode operation. LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the transmit ...
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ST16C552/552A Figure 6, INTERNAL LOOP-BACK MODE DIAGRAM D0-D7 -IOR -IOW -RESET BIDEN A0-A2 -CSA -CSB -CSP INT A,B INTP -RXRDY -TXRDY Rev. 3.40 Transmit Transmit FIFO Shift Registers Register Receive Receive FIFO Shift Registers Register Printer Data Ports Printer Control ...
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Printer Port The 552/552A contains a general purpose 8-bit parallel interface port that is designed to directly interface with a CENTRONICS Printer. A number of the control/ interrupt signals and the 8-bit data bus have been designed as bi-directional data ...
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ST16C552/552A REGISTER FUNCTIONAL DESCRIPTIONS The following table delineates the assigned bit functions for the eighteen 552/552A internal registers. The assigned bit functions are more fully defined in the following paragraphs. Table 7, ST16C552/552A INTERNAL REGISTERS Register BIT-7 ...
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Register BIT-7 [Default] Note 5* Printer Port Register Set: Note 3* [ PR[00] bit-7 [ PR[00] bit-7 [ SR[4F] -Busy [ IOSEL bit-7 [ COM[E0] logic “1” ...
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ST16C552/552A Interrupt Enable Register (IER) The Interrupt Enable Register (IER) masks the inter- rupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the INT A,B output pins. IER Vs Receive ...
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IER BIT 6-7: Not Used - initialized to a logic 0. FIFO Control Register (FCR) This register is used to enable the FIFO’s, clear the FIFO’s, set the receive FIFO trigger levels, and select the DMA mode. The DMA, and ...
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ST16C552/552A FCR BIT 4-5: Not Used - initialized to a logic 0. FCR BIT 6-7: (logic 0 or cleared is the default condi- tion, RX trigger level = 1) These bits are used to set the trigger level for the ...
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ISR BIT-0: Logic interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. Logic interrupt pending. (normal default condi- tion) ISR BIT 1-3: (logic 0 ...
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ST16C552/552A LCR LCR LCR Parity selection Bit-5 Bit-4 Bit parity Odd parity Even parity Force parity odd parity Forced even parity LCR BIT-6: When ...
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LSR BIT-2: Logic parity error. (normal default condition) Logic 1 = Parity error. The receive character does not have correct parity information and is suspect. In the FIFO mode, this error is associated with the character at ...
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ST16C552/552A MSR BIT-6: RI (active high, logical 1). Normally this bit is the compliment of the -RI input. In the loop-back mode this bit is equivalent to MCR bit-2 in the MCR register. MSR BIT-7: CD (active high, logical 1). ...
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COM bit-1 is used to read status while CON bit 1 is used to set an output state function as an ...
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ST16C552/552A Logic 0 = -SLCTIN output is set to a logic 1. (normal default condition) Logic 1 = -SLCTIN output is set to a logic 0. CON BIT-4: This bit enables or masks the printer interrupt output -INTP. The state ...
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AC ELECTRICAL CHARACTERISTICS (-40 - +85 C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. A Symbol Parameter T ,T Clock pulse duration Oscillator/Clock frequency 3w T ...
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ST16C552/552A ABSOLUTE MAXIMUM RATINGS Supply range Voltage at any pin Operating temperature Storage temperature Package dissipation DC ELECTRICAL CHARACTERISTICS (-40 - +85 C for Industrial grade packages), Vcc=2.97 - 5.5V unless otherwise specified. A Symbol ...
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Add r ess - A0- -IOW D 0-D 7 Rev. 3. ...
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ST16C552/552A T2w EXTERNAL CLOCK -IOW Active -RTS Change of state -DTR -CD -CTS -DSR INT -IOR -RI Rev. 3.40 T1w T3w External clock timing T17d Change of state Change of state T18d Active T19d Active Modem input/output timing 30 EX-CK-1 ...
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START BIT RX INT -IOR Rev. 3.40 ST16C552/552A DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK Receive timing 31 STOP BIT D6 D7 PARITY NEXT BIT ...
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ST16C552/552A START BIT RX -RXRDY -IOR Receive ready timing in none FIFO mode Rev. 3.40 DATA BITS (5- STOP BIT D6 D7 PARITY NEXT BIT DATA START BIT T25d Active Data Ready T26d ...
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START BIT RX -RXRDY -IOR Rev. 3.40 ST16C552/552A DATA BITS (5- Receive timing in FIFO mode 33 STOP BIT D6 D7 PARITY First byte BIT that reaches the trigger level T25d Active Data Ready ...
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ST16C552/552A START BIT TX INT -IOW Active Rev. 3.40 DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS T23d 16 BAUD RATE CLOCK Transmit timing 34 STOP BIT PARITY ...
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START BIT TX -IOW Active D0-D7 BYTE #1 -TXRDY Transmit ready timing in none FIFO mode Rev. 3.40 ST16C552/552A DATA BITS (5- T27d Active Transmitter ready 35 STOP BIT D6 D7 PARITY NEXT BIT ...
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ST16C552/552A START BIT TX -IOW Active D0-D7 BYTE #16 T27d -TXRDY Transmit ready timing in FIFO mode Rev. 3.40 DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS T28d FIFO Full ...
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T40d INTP -IOR T40s NORMAL MODE INTSEL PD0-PD7 Rev. 3.40 T39w INTERRUPT LATCHED MODE SELECT T41h VALID DATA Printer port timing (552 only) 37 ST16C552/552A T42d T43d X552-PR-1 ...
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ST16C552/552A -ACK T40d INTP -IOR T40s NORMAL MODE INTSEL PD0-PD7 Rev. 3.40 T39w INTERRUPT LATCHED MODE SELECT T41h VALID DATA Printer port timing (552A only) 38 T42d T43d X552-PR-2 ...
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... While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized ...