ST16C552CJ68-F Exar Corporation, ST16C552CJ68-F Datasheet - Page 11

• Manufacturer Part Number: ST16C552CJ68-F
• Description: IC UART FIFO PAR 16B DUAL 68PLCC
• Manufacturer: Exar Corporation
• Type: Dual UART with 16-byte FIFOs and Parallel Printer Portr

Specifications of ST16C552CJ68-F

• Number Of Channels: 2, DUART
• Package / Case: 68-LCC (J-Lead)
• Features: *
• Fifo's: 16 Byte
• Protocol: Printer
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Parallel Port: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1.5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 3 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 2
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1263-5

FIFO Operation
The 16 byte transmit and receive data FIFO’s are
enabled by the FIFO Control Register (FCR) bit-0. The
user can set the receive trigger level via FCR bits 6/
7 but not the transmit trigger level. The transmit
interrupt trigger level is set to 16 following a reset. The
receiver FIFO section includes a time-out function to
ensure data is delivered to the external CPU. An
interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the load-
ing of a character or the receive trigger level has not
been reached.
Hardware/Software and Time-out Interrupts
The interrupts are enabled by IER bits 0-3. Care must be
taken when handling these interrupts. Following a reset
the transmitter interrupt is enabled, the 552/552A will
issue an interrupt to indicate that transmit holding
register is empty. This interrupt must be serviced prior
to continuing operations. The LSR register provides the
current singular highest priority interrupt only. It could
be noted that CTS and RTS interrupts have lowest
interrupt priority. A condition can exist where a higher
priority interrupt may mask the lower priority CTS/RTS
interrupt(s). Only after servicing the higher pending
interrupt will the lower priority CTS/ RTS interrupt(s) be
reflected in the status register. Servicing the interrupt
without investigating further interrupt conditions can
result in data errors.
When two interrupt conditions have the same priority,
it is important to service these interrupts correctly.
Receive Data Ready and Receive Time Out have the
same interrupt priority (when enabled by IER bit-3).
The receiver issues an interrupt after the number of
characters have reached the programmed trigger
level. In this case the 552/552A FIFO may hold more
characters than the programmed trigger level. Follow-
ing the removal of a data byte, the user should recheck
LSR bit-0 for additional characters. A Receive Time
Out will not occur if the receive FIFO is empty. The time
out counter is reset at the center of each stop bit
received or each time the receive holding register (RHR)
is read (see Figure 4, Receive Time-out Interrupt). The
actual time out value is T (Time out length in bits) = 4 X
Rev. 3.40
11
P (Programmed word length) + 12. To convert the time
out value to a character value, the user has to consider
the complete word length, including data information
length, start bit, parity bit, and the size of stop bit, i.e.,
1X, 1.5X, or 2X bit times.
Example -A: If the user programs a word length of 7,
with no parity and one stop bit, the time out will be:
T = 4 X 7( programmed word length) +12 = 40 bit times.
The character time will be equal to 40 / 9 = 4.4
characters, or as shown in the fully worked out ex-
ample: T = [(programmed word length = 7) + (stop bit
= 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) =
4.4 characters.
Example -B: If the user programs the word length = 7,
with parity and one stop bit, the time out will be:
T = 4 X 7(programmed word length) + 12 = 40 bit times.
Character time = 40 / 10 [ (programmed word length
= 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4
characters.
Programmable Baud Rate Generator
The 552/552A supports high speed modem technolo-
gies that have increased input data rates by employing
data compression schemes. For example a 33.6Kbps
modem that employs data compression may require a
115.2Kbps input data rate. A 128.0Kbps ISDN modem
that supports data compression may need an input
data rate of 460.8Kbps. The 552/552A can support a
standard data rate of 921.6Kbps.
Single baud rate generator is provided for the trans-
mitter and receiver, allowing independent TX/RX
channel control. The programmable Baud Rate Gen-
erator is capable of accepting an input clock up to 24
MHz, as required for supporting a 1.5Mbps data rate.
The 552/552A requires that an external clock source
be connected to the CLK input pin to clock the internal
baud rate generator for standard or custom rates. (see
Baud Rate Generator Programming below).
The generator divides the input 16X clock by any divisor
from 1 to 2
clock by 16. The basic 16X clock provides table rates to
support standard and custom applications using the
16
-1. The 552/552A divides the basic external
ST16C552/552A