XR16C854IV-F Exar Corporation, XR16C854IV-F Datasheet - Page 24

• Manufacturer Part Number: XR16C854IV-F
• Description: IC UART FIFO 128B QUAD 64LQFP
• Manufacturer: Exar Corporation
• Type: Quad UART with 128-byte FIFOsr

Specifications of XR16C854IV-F

• Number Of Channels: 4, QUART
• Package / Case: 64-LQFP
• Features: *
• Fifo's: 128 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 3 mA to 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 45 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.97 V to 5.5 V
• No. Of Channels: 4
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1276

XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
.
A
A2-A0
DDRESS
1 1 1
1 1 1
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
T
ABLE
EMSR
N
FLVL
MCR
MSR
RHR
THR
FCR
SPR
LCR
LSR
R
IER
ISR
AME
EG
9: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR Divisor
RD/WR
RD/WR
R
W
WR
WR
WR
RD
RD
RD
RD
RD
EAD
RITE
/
RX FIFO
RX FIFO
Enabled
Enable
Trigger
Enable
Global
FIFOs
CTS#
B
Pres-
Rsvd
BRG
caler
Error
Input
Bit-7
Bit-7
Bit-7
Bit-7
CD#
Int.
IT
0/
0/
-7
RX FIFO
IR Mode
Enabled
ENable
Enable
Trigger
Set TX
THR &
Empty
FIFOs
RTS#
Break
B
Rsvd
Input
Bit-6
Bit-6
TSR
Bit-6
Bit-6
RI#
Int.
IT
0/
0/
-6
16C550 Compatible Registers
TX FIFO
Set Par-
XonAny
Xoff Int.
Enable
Source
Trigger
Empty
DSR#
B
Hyst.
Input
Bit-5
Bit-5
Bit-5
THR
Bit-5
Auto
RTS
Bit-5
INT
bit-3
ity
IT
0/
0/
0/
0/
-5
24
TX FIFO
Lopback
Internal
Source
Enable
Trigger
Enable
Sleep
Mode
Parity
Break
CTS#
B
Even
Input
Hyst.
Bit-4
Bit-4
Bit-4
Bit-4
Auto
RTS
Bit-4
INT
bit-2
RX
IT
0/
0/
0/
-4
S
HADED BITS ARE ENABLED WHEN
RX Fram-
INT Out-
ing Error
Stat. Int.
Modem
Enable
Source
Enable
Enable
Enable
(OP2#)
Mode
Parity
B
Delta
DMA
Rsvd
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
CD#
INT
put
IT
-3
RX Line
Enable
Source
(OP1#)
Reset
Parity
B
FIFO
Rsvd
Delta
Rsvd
Error
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Stat.
Stop
INT
Bits
RI#
Int.
RX
TX
IT
-2
Source
Control
Enable
Length
Output
Empty
Reset
DSR#
Count
RTS#
Over-
Rx/Tx
Word
B
FIFO
Error
Delta
FIFO
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
INT
run
TX
RX
RX
Int
IT
-1
Control
Enable
Source
Enable
EFR B
Length
Output
Ready
FIFOs
DTR#
CTS#
Rx/Tx
Count
B
Word
Delta
FIFO
Bit-0
Bit-0
Data
Bit-0
Bit-0
Data
Bit-0
Bit-0
INT
RX
Int.
RX
xr
IT
-0
IT
-4=1
FCTR[6]=0
FCTR[6]=1
LCR[7] = 0
LCR[7] = 0
LCR[7] = 0
LCR[7] = 0
C
REV. 3.0.1
OMMENT