XR16C854IV-F Exar Corporation, XR16C854IV-F Datasheet - Page 29

• Manufacturer Part Number: XR16C854IV-F
• Description: IC UART FIFO 128B QUAD 64LQFP
• Manufacturer: Exar Corporation
• Type: Quad UART with 128-byte FIFOsr

Specifications of XR16C854IV-F

• Number Of Channels: 4, QUART
• Package / Case: 64-LQFP
• Features: *
• Fifo's: 128 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 3 mA to 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 45 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.97 V to 5.5 V
• No. Of Channels: 4
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1276

xr
REV. 3.0.1
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
•
•
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load.
must be set to ‘1’ before these bits can be accessed. Note that the receiver and the transmitter cannot use
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 5-4 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receive
FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the
trigger level.
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
FCTR
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
B
IT
0
0
-5
FCTR
B
IT
0
1
-4
Table 11
B
FCR
IT
0
0
1
1
0
0
1
1
-7
T
ABLE
shows the complete selections. Note that the receiver and the transmitter cannot use
B
FCR
IT
0
1
0
1
0
1
0
1
11: T
-6
RANSMIT AND
B
FCR
IT
0
0
0
1
1
-5
BIT
FCR
0
0
1
0
1
-4
R
ECEIVE
T
RIGGER
1 (default)
R
29
ECEIVE
14
16
24
28
FIFO T
4
8
8
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
L
EVEL
Table 11
RIGGER
1 (default)
T
T
RANSMIT
L
RIGGER
EVEL
16
24
30
below shows the selections. EFR bit-4
L
8
EVEL
S
ELECTION
Table-A. 16C550, 16C2550,
16C2552, 16C554, 16C580
compatible.
Table-B. 16C650A compatible.
C
OMPATIBILITY
XR16C854/854D