SC16C752BIB48,151 NXP Semiconductors, SC16C752BIB48,151 Datasheet - Page 21

IC DUAL UART 64BYTE 48LQFP

SC16C752BIB48,151

Manufacturer Part Number
SC16C752BIB48,151
Description
IC DUAL UART 64BYTE 48LQFP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SC16C752BIB48,151

Number Of Channels
2, DUART
Package / Case
48-LFQFP
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Voltage
2.25 V ~ 5.5 V
Data Rate
5 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.25 V
Supply Current
4.5 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V or 3.3 V or 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
935274411151
SC16C752BIB48-S
SC16C752BIB48-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SC16C752BIB48,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
SC16C752B
Product data sheet
7.1 Receiver Holding Register (RHR)
7.2 Transmit Holding Register (THR)
Remark: Refer to the notes under
The receiver section consists of the Receiver Holding Register (RHR) and the Receiver
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX terminal. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the Line Control Register. If the FIFO is disabled, location
zero of the FIFO is used to store the characters.
Remark: In this case, characters are overwritten if overflow occurs.
If overflow occurs, characters are lost. The RHR also stores the error status bits
associated with each character.
The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TXn
terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are
lost if overflow occurs.
All information provided in this document is subject to legal disclaimers.
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 6 — 30 November 2010
Table 9
for more register access information.
SC16C752B
© NXP B.V. 2010. All rights reserved.
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