71M6521FE-IGT/F Maxim Integrated Products, 71M6521FE-IGT/F Datasheet - Page 22

• Manufacturer Part Number: 71M6521FE-IGT/F
• Description: IC ENERGY METER 32K FLASH 64LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 71M6521FE-IGT/F

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register
P0
DIR0
P1
DIR1
P2
DIR2
All DIO ports on the chip are bi-directional. Each of them consists of a Latch (SFR ‘P0’ to ‘P2’), an output driver, and
an input buffer, therefore the MPU can output or read data through any of these ports. Even if a DIO pin is configured
as an output, the state of the pin can still be read by the MPU, for example when counting pulses issued via DIO pins
Table 12 shows the location and description of the 71M6521DE/DH/FE-specific SFRs.
Register
ERASE
PGADDR
EEDATA
EECTRL
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that are under CE control.
The technique of reading the status of or generating interrupts based on DIO pins configured as outputs,
can be used to implement pulse counting.
Special Function Registers Specific to the 71M6521DE/DH/FE
FLSH_ERASE
FLSH_PGADR
Address
Alternative
0xA2
0xA0
0xA1
0x80
0x90
0x91
SFR
Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
0x94
0xB7
0x9E
0x9F
SFR
Description
Register for port 0 read and write operations (pins DIO4…DIO7)
Data direction register for port 0. Setting a bit to 1 means that the corresponding pin is
an output.
Register for port 1 read and write operations (pins DIO8…DIO11, DIO14-DIO15)
Data direction register for port 1.
Register for port 2 read and write operations (pins DIO16…DIO17, DIO19…DIO21)
Data direction register for port 2.
R/W
R/W
R/W
R/W
W
Table 11: Port Registers
Description
This register is used to initiate either the Flash Mass Erase cycle or
the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle (default =
0x00).
0x55 – Initiate Flash Page Erase cycle. Must be preceded by a write
0xAA – Initiate Flash Mass Erase cycle. Must be preceded by a write
Any other pattern written to FLSH_ERASE will have no effect.
Flash Page Erase Address register containing the flash memory
page address (page 0 thru 127) that will be erased during the Page
Erase cycle (default = 0x00).
Must be re-written for each new Page Erase cycle.
I
I
byte of data to EEPROM, it places the data in EEDATA and then
writes the ‘Transmit’ code to EECTRL. The write to EECTRL initiates
the transmit sequence. See the EEPROM Interface section for a
description of the command and status bits available for EECTRL.
2
2
C EEPROM interface data register
C EEPROM interface control register. If the MPU wishes to write a
to FLSH_PGADR @ SFR 0xB7.
to FLSH_MEEN @ SFR 0xB2 and the debug port must be
enabled.
71M6521DE/DH/FE Data Sheet
Rev 2