71M6521FE-IGT/F Maxim Integrated Products, 71M6521FE-IGT/F Datasheet - Page 49

• Manufacturer Part Number: 71M6521FE-IGT/F
• Description: IC ENERGY METER 32K FLASH 64LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 71M6521FE-IGT/F

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

71M6521DE/DH/FE Data Sheet
Figure 16 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and the two
serial output streams. In this example, MUX_DIV=4 and FIR_LEN=1 (384). The duration of each MUX frame is 1 +
MUX_DIV * 2 if FIR_LEN=288, and 1 + MUX_DIV * 3 if FIR_LEN=384. An ADC conversion will always consume an
integer number of CK32 clocks. Followed by the conversions is a single CK32 cycle where the bandgap voltage is
allowed to recover from the change in CROSS.
Each CE program pass begins when ADC0 (channel IA) conversion begins. Depending on the length of the CE
program, it may continue running until the end of the ADC3 (VB) conversion. CE opcodes are constructed to ensure
that all CE code passes consume exactly the same number of cycles. The result of each ADC conversion is inserted
into the CE DRAM when the conversion is complete. The CE code is written to tolerate sudden changes in ADC data.
The exact CK count when each ADC value is loaded into DRAM is shown in Figure 16.
Figure 16 also shows that the serial RTM data stream begins transmitting at the beginning of state ‘S.’ RTM,
consisting of 140 CK cycles, will always finish before the next code pass starts.
Rev 2
TMUXOUT/RTM
RTM DATA0 (32 bits)
RTM DATA1 (32 bits)
RTM DATA2 (32 bits)
RTM DATA3 (32 bits)
ADC TIMING
RTM TIMING
CE TIMING
ADC EXECUTION
CE_EXECUTION
MUX_SYNC
NOTES:
XFER_BUSY
MUX STATE
MUX_SYNC
CKTEST
CE_BUSY
CK32
Figure 16: Timing Relationship between ADC MUX, Compute Engine, and Serial Transfers.
CK32
RTM
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES.
FLAG
S
0
0
1
150
30
0
31
CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 5)
System Timing Summary
FLAG
ADC0
Figure 17: RTM Output Format
450
INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
MUX_DIV
0
1
1
Conversions, MUX_DIV=1 (4 conversions) is shown
30
31
ADC MUX Frame
ADC1
FLAG
900
0
2
1
30
31
ADC2
1350
FLAG
MAX CK COUNT
3
0
1
30
ADC3
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31
1800
Settle
140
S