71M6521FE-IGT/F Maxim Integrated Products, 71M6521FE-IGT/F Datasheet - Page 75

• Manufacturer Part Number: 71M6521FE-IGT/F
• Description: IC ENERGY METER 32K FLASH 64LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 71M6521FE-IGT/F

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

71M6521DE/DH/FE Data Sheet
Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially stored in
flash memory and copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are
mapped to the MPU SFR memory space. The remaining bits are mapped to the address range 0x2xxx. Bits with R
(read) direction can be read by the MPU. Columns labeled “Rst” and “Wk” describe the bit values upon reset and
wake, respectively. No entry in one of these columns means the bit is either read-only or is powered by the non-
volatile supply and is not initialized. Write-only bits will return zero when they are read.
Name
ADC_E
BME
CE_E
CE_LCTN[4:0]
CHOP_E[1:0]
CKOUT_E[1:0]
COMP_STAT[0]
DI_RPB[2:0]
DIO_R1[2:0]
DIO_R2[2:0]
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
DIO_DIR0[7:4,2:1]
Rev 2
Location
SFRA2
[7:4,2:0]
200C[2:0]
200C[6:4]
200D[2:0]
200D[6:4]
20A8[4:0]
2002[5:4]
2004[5,4]
2009[2:0]
2009[6:4]
200A[2:0]
200B[2:0]
200B[6:4]
200E[2:0]
200E[6:4]
2005[3]
2020[6]
2000[4]
2003[0]
I/O RAM DESCRIPTION – Alphabetical Order
Rst
31
00
--
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Wk
31
00
--
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
Dir
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Enables ADC and VREF. When disabled, removes bias current
Battery Measure Enable. When set, a load current is immediately
applied to the battery and it is connected to the ADC to be
measured on Alternative Mux Cycles. See MUX_ALT bit.
CE enable.
CE program location. The starting address for the CE program is
1024*CE_LCTN. CE_LCTN must be defined before the CE is en-
abled.
Chop enable for the reference bandgap circuit. The value of CHOP
will change on the rising edge of MUXSYNC according to the value
in CHOP_E:
1
CKTEST Enable. The default is 00
00-SEG19,
01-CK_FIR (5MHz Mission, 32kHz Brownout)
10-Not allowed (reserved for production test)
11-Same as 10.
The status of the power fail comparator for V1.
Connects dedicated I/O pins DIO2 and DIO4 through DIO11 as well
as input pins PB and DIO1 to internal resources. If more than one
input is connected to the same resource, the ‘MULTIPLE’ column
below specifies how they are combined.
Programs the direction of pins DIO7-DIO4 and DIO2-DIO1. 1 indi-
cates output. Ignored if the pin is not configured as I/O. See
DIO_PV and DIO_PW for special option for DIO6 and DIO7 outputs.
See DIO_EEX for special option for DIO4 and DIO5.
00-toggle
except at the mux sync edge at the end of SUMCYCLE.
DIO_Rx
000
001
010
011
100
101
110
111
1
Resource
NONE
Reserved
T0 (Timer0 clock or gate)
T1 (Timer1 clock or gate)
High priority IO interrupt (int0 rising)
Low priority IO interrupt (int1 rising)
High priority IO interrupt (int0 falling)
Low priority IO interrupt (int1 falling)
01-positive
10-reversed
11-toggle
Page: 75 of 107
MULTIPLE
OR
OR
OR
OR
OR
OR
OR
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