XRP7714ILB-F Exar Corporation, XRP7714ILB-F Datasheet - Page 18

• Manufacturer Part Number: XRP7714ILB-F
• Description: IC CTRLR PWM/LDO STP-DWN 40TQFN
• Manufacturer: Exar Corporation
• Type: Step-Down (Buck)r

Specifications of XRP7714ILB-F

• Number Of Outputs: 4
• Package / Case: 40-WFQFN Exposed Pad
• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Voltage - Output: 0.9 ~ 5.1 V
• Frequency - Switching: 300kHz ~ 1.5MHz
• Voltage - Input: 4.75 ~ 25 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Switching Frequency: 300 KHz
• Operating Supply Voltage: 4.75 V to 25 V
• Supply Current: 28 mA to 50 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Output Voltage: 0.9 V to 5.1 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 1016-1350 - EVAL BAORD FOR XRP77141016-1344 - IN-SOCKET PROG BRD VIA USB/GUI
• Current - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1016-1351

S
The SET_PD_FALL_CHx register is a 16 bit register. This register specifies the soft-stop delay and
ramp (fall-time) characteristics for when the chip receives a channel disable indication from the
Host to shutdown the channel.
Bits [15:10] specify the delay after disabling a channel but before starting the shutdown of the
channel; where each bit represents 250µs steps. Bits [9:0] specify the fall time of the channel;
these 10 bits define the number of microseconds for each 50mV increment to reach the discharge
threshold.
P
The XRP7714 allows the user to set the upper and lower bound for a power good signal per
channel.
SET_PWRG_TARG_MIN_CHx register sets the lower bound. Each register has a 20mV LSB
resolution. When the output voltage is within bounds the power good signal is asserted high.
Typically the upper bound should be lower than the over-voltage threshold. In addition, the power
good signal can be delayed by a programmable amount set in the SET_PWRGD_DLY_CHx register.
The power good delay is only set after the soft-start period is finished. If the channel has a pre-
charged condition that falls into the power good region, a power good flag is not set until the soft-
start is finished.
PWM S
The PWM switching frequency is set by choosing the corresponding oscillator frequency and clock
divider ratio in the SET_SW_FREQUENCY register. Bits [6:4] set the oscillator frequency and bits
© 2010 Exar Corporation
OFT
OWER
-S
TOP
G
WITCHING
OOD
The
F
LAG
SET_PWRG_TARG_MAX_CHx
F
REQUENCY
Enable
Signal
Vout
Ena ble
Signal
Vout
Q
Q
Fig. 23: Channel Power Up Sequence
Fig. 24: Channel Soft-Stop Sequence
u
u
a
a
d
d
Bit [15 :10]
DELAY
C
C
Bit [15:10]
DELAY
h
h
a
a
18/27
n
n
n
n
SS_RISE_CHx
REGISTER
PD_DELAY_CHx
e
e
register
REGISTER
l
l
D
D
i
i
g
g
i
i
t
t
a
a
FALL TIME
Bit [9:0]
RISE TIME
Bit [9:0]
l
l
sets
P
P
W
W
M
M
the
S
S
t
t
e
e
p
p
upper
D
D
o
o
w
w
n
n
X
X
bound,
C
C
R
R
o
o
n
P
n
P
Rev. 1.1.3
t
t
7
7
r
r
o
7
o
7
l
l
1
1
l
l
the
e
e
4
4
r
r