STEVAL-IHM029V1 STMicroelectronics, STEVAL-IHM029V1 Datasheet - Page 13

• Manufacturer Part Number: STEVAL-IHM029V1
• Description: BOARD DEMO MOTOR CTRL VIPER16L
• Manufacturer: STMicroelectronics
• Series: VIPer™ plusr
• Type: Other Power Managementr

Specifications of STEVAL-IHM029V1

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: STM8S103F2, T1235H
• Primary Attributes: Universal Motor Control, 90 ~ 265 VAC Input, 2000 W Output
• Secondary Attributes: LED Status Indicators
• Operating Supply Voltage: 90 V to 265 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: STM8S103F2
• Other names: 497-10752

STM8S103K3 STM8S103F3 STM8S103F2
4.5
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated,
any attempt to toggle its status triggers a global erase of the program and data memory. Even
if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.
Clock controller
The clock controller distributes the system clock (f
to the core and the peripherals. It also manages clock gating for low power modes and ensures
clock robustness.
Features
•
•
•
•
Clock prescaler: To get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock source
is ready. The design guarantees glitch-free switching.
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Master clock sources: Four different clock sources can be used to drive the master
clock:
-
1-16 MHz high-speed external crystal (HSE)
Low density
Flash program
memory
(8 Kbytes)
Data
EEPROM
memory
Figure 2: Flash memory organization
DocID15441 Rev 6
Remains write protected during IAP
Data memory area ( 640 bytes)
Write access possible for IAP
Program memory area
Option bytes
UBC area
MASTER
) coming from different oscillators
Programmable
area from 64
bytes(1 page)
up to 8 Kbytes
(in 1 page steps)
Product overview
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