73M1903C-EVM Maxim Integrated Products, 73M1903C-EVM Datasheet - Page 11

• Manufacturer Part Number: 73M1903C-EVM
• Description: BOARD DEMO 73M1903C WORLDWIDE
• Manufacturer: Maxim Integrated Products

Specifications of 73M1903C-EVM

• Main Purpose: Interface, Analog Front End (AFE)
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -

DS_1903C_033
73M1903C Data Sheet
Up to eight 73M1903C devices may be daisy-chained if the control frame sync is placed at the middle of
the data frame sync interval. Four devices may be daisy-chained if the control frame sync is placed at the
1/4 of the data frame sync interval. In all cases involving slave and daisy chain operation, only hardware
controlled Control Frames are supported. Software requested control frames are not allowed.
In slave mode the relationship of Fs and Fsclk is Fsclk/Fs, with a range of from 96 to 256 SCLKs per Fs.
Again, the host controls the relationship of FS to SCLK, with the condition that Fsclk>750 kHz and
Fsys=4608*Fs. The 79M1903C PLL must be programmed to generate Fsys with those conditions. To
program the 73M1903C NCOs, OSCIN (Fsclk)=SCLK=Fref when Pdvsr=1 and Prst=0 in the calculations.
Fsys in the previous discussion is Fvco in the calculations which is equal to 4608*Fs. For example, two
typical cases are Fsclk=256*Fs and Fsclk=144*Fs.
For the case when Fsclk=256*Fs and Fs=8 kHz, the 79M1903C PLL has to be set to
Fsys=4608*Fs=36.864 MHz, and Sclk=256*8 kHz=2.048 MHz. Therefore Ndvsr=36.864/2.048=18 (12h)
and Nrst=0
For the case when Fsclk=144*Fs and d Fs=8 kHz, the 79M1903C PLL has to be set to
Fsys=4608*Fs=36.864 MHz and Sclk=144*8 kHz=1.152 MHz. Therefore Ndvsr=36.864/1.152=32 (20h)
and Nrst=0
Rev. 5.0
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