73M1903C-EVM Maxim Integrated Products, 73M1903C-EVM Datasheet - Page 16
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73M1903C-EVM
Manufacturer Part Number
73M1903C-EVM
Description
BOARD DEMO 73M1903C WORLDWIDE
Manufacturer
Maxim Integrated Products
Specifications of 73M1903C-EVM
Main Purpose
Interface, Analog Front End (AFE)
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Embedded
-
73M1903C Data Sheet
5 PLL Configuration Registers
Register08 (PLL_PSEQ): Address 08h
Reset State 00h
Pseq(7:0)
Register09 (PLL_RST): Address 09h
Reset State 0Ah
Prst(2:0) represents the rate at which the sequence register is reset.
Pdvsr(4:0) represents the divisor.
Register0A (PLL_KVCO): Address 0Ah
Reset State 22h
Ichp(3:0)
Bit 3 is a reserved control bit. This bit shall remain 0 always.
Kvco(2:0)
16
Bit 7
Bit 7
Bit 7
(0X0A[:47]) represents the size of the charge pump current in the PLL. This charge pump
current can be calculated with Ichp = 2.0μA* (2 + Ichp0 + Ichp1 * 2
(T/To), where To=300 C° and T=Temperature in K°.
(0X0A[2:0]) Represents the magnitude of Kvco associated with the VCO within PLL.
Prst(2:0)
(0X08[7:0])
Register09 is 00, this register is ignored.
Bit 6
Bit 6
Bit 6
Kvco2
Ichp(3:0)
0
0
0
0
1
1
1
1
Bit 5
Bit 5
Bit 5
Table 3: Fvco and Kvco Settings at 25°C
Kvco1
This corresponds to the sequence of divisor. If Prst(2:0) setting in
0
0
1
1
0
0
1
1
Bit 4
Bit 4
Bit 4
Pseq(7:0)
Kvco0
Reserved
0
1
0
1
0
1
0
1
Bit 3
Bit 3
Bit 3
Pdvsr(4:0)
Bit 2
Bit 2
33 MHz
36 MHz
44 MHz
48 MHz
57 MHz
61 MHz
69 MHz
73 MHz
Bit 2
Fvco
Kvco(2:0)
Bit 1
Bit 1
Bit 1
38 MHz/v
38 MHz/v
40 MHz/v
40 MHz/v
63 MHz/v
63 MHz/v
69 MHz/v
69 MHz/v
1
+ Ichp2 * 2
Kvco
Bit 0
Bit 0
Bit 0
DS_1903C_033
2
+Ichp3 * 2^3 )*
Rev. 5.0