73M1903C-EVM Maxim Integrated Products, 73M1903C-EVM Datasheet - Page 17

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73M1903C-EVM

Manufacturer Part Number
73M1903C-EVM
Description
BOARD DEMO 73M1903C WORLDWIDE
Manufacturer
Maxim Integrated Products
Datasheets

Specifications of 73M1903C-EVM

Main Purpose
Interface, Analog Front End (AFE)
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Embedded
-
DS_1903C_033
Register0B (PLL_DIV): Address 0Bh
Reset State 12h
Ndvsr(6:0)
Register0C (PLL_SEQ): Address 0Ch
Reset State 00h
Nseq(7:0)
Register0D (XTAL_BIAS): Address 0Dh
Reset State 48h
Xtal(1:0)
Nrst(2:0)
Rev. 5.0
Unused
Bit 7
Bit 7
Bit 7
Xtal(1:0)
(0X0D[7:6]) Crystal Oscillator bias current selection
00 = Xtal osc. bias current at 120 μA
01 = Xtal osc. bias current at 180 μA
10 = Xtal osc. bias current at 270 μA
11 = Xtal osc. bias current at 450 μA
If OSCIN is used as a Clock input, the 00 setting should be used to save power.
(0X0D[2:0]) Represents the rate at which the NCO sequence register is reset.
The address 0Dh must be the last register to be written to when effecting a change in PLL.
Bit 6
Bit 6
Bit 6
(0X0B[6:0])
(0X0C[7:0])
Bit 5
Bit 5
Bit 5
Reserved
Represents the divisor. If Nrst{2:0] =0 this register is ignored.
Represents the divisor sequence.
Bit 4
Bit 4
Bit 4
Nseq(7:0)
Ndvsr(6:0)
Bit 3
Bit 3
Bit 3
Bit 2
Bit 2
Bit 2
Nrst(2:0)
Bit 1
Bit 1
Bit 1
73M1903C Data Sheet
Bit 0
Bit 0
Bit 0
17

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