ATA5773-DK1 Atmel, ATA5773-DK1 Datasheet - Page 113

• Manufacturer Part Number: ATA5773-DK1
• Description: BOARD XMITTER FOR ATA5773 315MHZ
• Manufacturer: Atmel
• Type: Transmitterr

Specifications of ATA5773-DK1

• Frequency: 315MHz
• Maximum Frequency: 315 MHz
• Supply Voltage (max): 4 V
• Supply Voltage (min): 2 V
• Supply Current: 9 mA
• Product: RF Development Tools
• For Use With/related Products: ATA5773
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9137E–RKE–12/10
Figure 4-45. Phase and Frequency Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x
Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or
ICR1 is used for defining the TOP value, the OC1A or ICF1 flag set when TCNT1 has reached
TOP. The interrupt flags can then be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.
As
rical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the
rising and the falling slopes will always be equal. This gives symmetrical output pulses and is
therefore frequency correct.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. How-
ever, if the base PWM frequency is actively changed by changing the TOP value, using the
OCR1A as TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM
waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted
PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (See
Table 4-41 on page
direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by
setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1
when the counter increments, and clearing (or setting) the OC1x Register at compare match
between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the out-
put when using phase and frequency correct PWM can be calculated by the following
equation:
Figure 4-45
TCNTn
OCnx
OCnx
Period
shows the output generated is, in contrast to the phase correct mode, symmet-
117). The actual OC1x value will only be visible on the port pin if the data
1
f
OCnxPFCPWM
2
=
3
---------------------------------
2
f
clk_I/O
N
Atmel ATA5771/73/74
TOP
4
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)
113