ATA5773-DK1 Atmel, ATA5773-DK1 Datasheet - Page 132

• Manufacturer Part Number: ATA5773-DK1
• Description: BOARD XMITTER FOR ATA5773 315MHZ
• Manufacturer: Atmel
• Type: Transmitterr

Specifications of ATA5773-DK1

• Frequency: 315MHz
• Maximum Frequency: 315 MHz
• Supply Voltage (max): 4 V
• Supply Voltage (min): 2 V
• Supply Current: 9 mA
• Product: RF Development Tools
• For Use With/related Products: ATA5773
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.18.3.5
4.18.3.6
4.18.4
4.18.4.1
4.18.4.2
4.18.4.3
4.18.4.4
4.18.4.5
132
Atmel ATA5771/73/74
Alternative USI Usage
Start Condition Detector
Clock speed considerations
Half-duplex Asynchronous Data Transfer
4-bit Counter
12-bit Timer/Counter
Edge Triggered External Interrupt
Software Interrupt
The start condition detector is shown in
the range of 50 to 300ns) to ensure valid sampling of the SCL line. The start condition detector
is only enabled in Two-wire mode.
The start condition detector is working asynchronously and can therefore wake up the proces-
sor from the Power-down sleep mode. However, the protocol used might have restrictions on
the SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time
set by the CKSEL Fuses (see
32) must also be taken into the consideration. See the USISIF bit description in
4.18.5.3 “USISR – USI Status Register” on page 133
Maximum frequency for SCL and SCK is f
receieve rate in both two- and three-wire mode. In two-wire slave mode the Two-wire Clock
Control Unit will hold the SCL low until the slave is ready to receive more data. This may
reduce the actual data rate in two-wire mode.
When the USI unit is not used for serial communication, it can be set up to do alternative tasks
due to its flexible design.
By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact
and higher performance UART than by software only.
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will generate an increment.
Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit
counter.
By setting the counter to maximum value (F) it can function as an additional external interrupt.
The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This fea-
ture is selected by the USICS1 bit.
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
Section 4.9.1 “Clock Systems and their Distribution” on page
Figure 4-57 on page
CK
/4. This is also the maximum data transmit and
for further details.
131. The SDA line is delayed (in
9137E–RKE–12/10
Section