TEF6606T/V5,512 NXP Semiconductors, TEF6606T/V5,512 Datasheet
TEF6606T/V5,512
Specifications of TEF6606T/V5,512
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TEF6606T/V5,512 Summary of contents
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LPC3152/3154 ARM926EJ microcontrollers with USB High-speed OTG, SD/MMC, NAND flash controller, and audio codec Rev. 0.12 — 27 May 2010 1. General description The NXP LPC3152/3154 combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0 OTG, 192 kB SRAM, ...
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... NXP Semiconductors Three-channel 10-bit ADC Integrated 4/8/16-bit 6800/8080 compatible LCD interface Integrated audio codec with stereo ADC and Class AB headphone amplifier System functions Dynamic clock gating and scaling Multiple power domains Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB ...
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... NXP Semiconductors 3.1 Ordering options Table 2. Ordering options for LPC3152/54 Type number Total NAND SRAM Flash Controller LPC3152FET208 192 kB yes LPC3154FET208 192 kB yes LPC3152_3154 Preliminary data sheet Security High-speed 10-bit engine USB ADC AES channels no Device/ 3 Host/OTG yes Device/ 3 Host/OTG All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 4. Block diagram TEST/DEBUG INTERFACE ARM926EJ-S slave INTERRUPT CONTROLLER slave MPMC slave slave MCI SD/SDIO slave AHB TO APB BRIDGE 0 WDT SYSTEM CONTROL CGU IOCONFIG 10-bit ADC EVENT ROUTER RNG OTP TIMER 0/1/2/3 PWM (1) AES decryption engine available in LPC3154 only. Fig 1. ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. LPC3152/3154 pinning TFBGA208 package Table 3. Pin allocation table Pin names with prefix m are multiplexed pins. See Pin Symbol Pin Symbol Row A 1 n.c. 2 EBI_A_1_CLE 5 VSSE_IOC 6 VDDI 9 I2C_SCL0 10 FFAST_IN 13 ADC10B_GNDA 14 VSSE_IOC 17 n.c. - Row B 1 n.c. ...
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... NXP Semiconductors Table 3. Pin allocation table …continued Pin names with prefix m are multiplexed pins. See Pin Symbol Pin Symbol 5 mNAND_RYBN2 6 mGPIO8 9 SPI_CS_IN 10 PWM_DATA 13 n.c. 14 HP_OUTC 17 PSU_VSSA_CLEAN - Row E 1 VSSE_IOA 2 EBI_D_12 14 HP_VREF 15 RSTIN_N Row F 1 n.c. 2 EBI_D_13 14 TDO 15 DAC_VREFN Row G 1 n.c. ...
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... NXP Semiconductors Table 3. Pin allocation table …continued Pin names with prefix m are multiplexed pins. See Pin Symbol Pin Symbol 9 I2SRX_WS0 10 UART_RXD 13 GPIO0 14 ADC_VINR 17 UOS_CX1 - Row T 1 USB_DP 2 USB_GNDA 5 mLCD_DB_7 6 mLCD_DB_2 9 I2SRX_BCK0 10 TDI 13 mI2STX_DATA0 14 GPIO1 17 ADC_VREFP - Row U 1 n.c. 2 mLCD_DB_14 5 mLCD_DB_8 6 mLCD_DB_4 ...
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... NXP Semiconductors Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See TFBGA pin name TFB Digital GA I/O ball level [1] ADC_VREFN R16 - ADC_VREFP T17 - ADC_VDDA18 N15 SUP2 ADC_VDDA33 N14 SUP3 ADC_GNDA N16 - Audio Stereo DAC DAC_VDDA33 C14 SUP3 DAC_VREFP ...
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... NXP Semiconductors Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See TFBGA pin name TFB Digital GA I/O ball level [1] JTAG JTAGSEL U10 SUP3 TDI T10 SUP3 TRST_N U11 SUP3 TCK U12 SUP3 TMS U9 SUP3 TDO F14 SUP3 UART ...
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... NXP Semiconductors Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See TFBGA pin name TFB Digital GA I/O ball level [1] VDDE_IOC U15; SUP3 A15; A4; VDDE_IOD G15 SUP3 VSSE_IOA E1 VSSE_IOB K1 VSSE_IOC U16; - A14; A5; VSSE_IOD L14 - LCD interface [4] mLCD_CSB R8 SUP8 [4] mLCD_E_RD ...
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... NXP Semiconductors Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See TFBGA pin name TFB Digital GA I/O ball level [1] [4] I2SRX_BCK0 T9 SUP3 [4] I2SRX_WS0 R9 SUP3 2 I S/Digital audio output [4] mI2STX_DATA0 T13 SUP3 [4] mI2STX_BCK0 T12 SUP3 [4] mI2STX_WS0 R12 SUP3 [4] mI2STX_CLK0 ...
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... NXP Semiconductors Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See TFBGA pin name TFB Digital GA I/O ball level [1] [4] EBI_D_14 G2 SUP4 [4] EBI_D_15 H2 SUP4 [4] EBI_DQM_0_NOE K3 SUP4 [4] EBI_NWE K4 SUP4 [4] NAND_NCS_0 L2 SUP4 [4] NAND_NCS_1 L3 SUP4 [4] NAND_NCS_2 L4 SUP4 [4] NAND_NCS_3 M2 SUP4 [4] mNAND_RYBN0 B5 SUP4 ...
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... NXP Semiconductors Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See TFBGA pin name TFB Digital GA I/O ball level [1] PSU_STOP D15 SUP3 PSU_VBAT1 H17 SUP6 PSU_VBAT2 F17 SUP6 PSU_VBAT E16 SUP6 Li-Ion charger CHARGE_VNTC J17 - CHARGE_VSS J15 - CHARGE_CC_REF ...
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... NXP Semiconductors Table 5: Supply domains Supply Voltage range domain SUP1 1 1.3 V SUP2 1 1.8 V SUP3 2 3.6 V SUP4 1. 1.95 V (in 1.8 V mode) 2 3.6 V (in 3.3 V mode) SUP5 4 5.5 V SUP6 3 4.2 V SUP7 1.8 V SUP8 1. 1.95 V (in 1.8 V mode) 2 3.6 V (in 3.3 V mode) [1] When the SDRAM is used, the supply voltage of the NAND flash, SDRAM, and the LCD interface must be the same, i.e. SUP4 and SUP8 should be connected to the same rail ...
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... NXP Semiconductors Table 6: Cell types I/O pad name Type Function PS1 vdde3v3 Peripheral supply PS2 vdde Peripheral supply CG1 vssco Core ground CG2 vssis Core ground PG1 vsse Peripheral ground 6. Functional description 6.1 ARM926EJ-S The processor embedded in the chip is the ARM926EJ- member of the ARM9 family of general-purpose microprocessors ...
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... NXP Semiconductors 6.2 Memory map LPC3152/3154 4 GB reserved 2 GB reserved NAND flash/AES buffer reserved interrupt controller reserved external SDRAM bank 0 reserved external SRAM bank 1 external SRAM bank 0 reserved USB OTG reserved MCI/SD/SDIO reserved MPMC configuration registers APB4 domain APB3 domain APB2 domain ...
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... NXP Semiconductors Table 7. Analog die register addresses (I Block PSU/Li-ion charger Audio codec RTC 6.3 JTAG The JTAG interface allows the incorporation of the LPC3152/3154 in a JTAG scan chain. This module has the following features: • ARM926 debug access • Boundary scan • ...
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... NXP Semiconductors (1) AES decoder available on LPC3154 only. Fig 4. Block diagram of the NAND flash controller This module has the following features: • Dedicated NAND flash interface with hardware controlled read and write accesses. • Wear leveling support with 516-byte mode. • Software controlled command and address transfers to support wide range of flash devices. • ...
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... NXP Semiconductors – Interrupts generated after completion of error correction task with three interrupt registers. – Error correction statistics distributed to ARM using interrupt scheme. – Interface is compatible with the ARM External Bus Interface (EBI). 6.5 Multi-Port Memory Controller (MPMC) The multi-port memory controller supports the interface to different memory types, for example: • ...
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... NXP Semiconductors 6.6 External Bus Interface (EBI) The EBI module acts as multiplexer with arbitration between the NAND flash and the SDRAM/SRAM memory modules connected externally through the MPMC. The main purpose for using the EBI module is to save external pins. However only data and address pins are multiplexed ...
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... NXP Semiconductors The boot ROM determines the boot mode based on the reset state of the GPIO0, GPIO1, and GPIO2 pins. To ensure that GPIO0, GPIO1 and GPIO2 pins come up as inputs, pins TRST_N and JTAGSEL must be low during power-on reset, see UM10315 JTAG chapter for details ...
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... NXP Semiconductors 6.9 Memory Card Interface (MCI) The MCI controller interface can be used to access memory cards according to the Secure Digital (SD) and Multi-Media Card (MMC) standards. The host controller can be used to interface to small form factor expansion cards compliant to the SDIO card standard as well. Finally, the MCI supports CE-ATA 1.1 compliant hard disk drives. ...
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... NXP Semiconductors • This module has its own, integrated DMA engine. USB-IF TestID for Hi-speed peripheral silicon and embedded host silicon: 40720018 6.11 DMA controller The DMA Controller can perform DMA transfers on the AHB bus without using the CPU. This module has the following features: • ...
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... NXP Semiconductors 6.12 Interrupt controller The interrupt controller collects interrupt requests from multiple devices, masks interrupt requests, and forwards the combined requests to the processor. The interrupt controller also provides facilities to identify the interrupt requesting devices to be served. This module has the following features: • ...
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... NXP Semiconductors ARM DMA 926EJ-S master MULTI-LAYER AHB MATRIX = master/slave connection supported by matrix (1) AES decryption engine is available on LPC3154 only. Fig 5. LPC3152/3154 AHB multi-layer matrix connections This module has the following features: LPC3152_3154 Preliminary data sheet USB-OTG AHB MASTER 3 slave 0 AHB-APB 0 BRIDGE 0 ...
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... NXP Semiconductors • Supports all combinations of 32-bit masters and slaves (fully connected interconnect matrix). • Round-Robin priority mechanism for bus arbitration: all masters have the same priority and get bus access in their natural order • Four devices on a master port (listed in their natural order for bus arbitration): – ...
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... NXP Semiconductors Within most clock domains, the output clocks are again grouped into one or more subdomains. All output clocks within one subdomain are either all generated by the same fractional divider or they are connected directly to the base clock. Therefore all output clocks within one subdomain have the same frequency and all output clocks within one clock domain are synchronous because they originate from the same base clock The CGU reference clock is generated by the external crystal ...
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... NXP Semiconductors • Based on the input of the Watchdog timer (see also generate a system-wide reset in the case of a system stall. clock resources EXTERNAL OSCILLATOR CRYSTAL I2SRX_BCK0 I2SRX_WS0 The LPC3152/3154 has 11 clock domains (n = 11). The number of fractional dividers depends on the clock domain. Fig 6. CGU block diagram 6 ...
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... NXP Semiconductors APB Fig 7. Block diagram of the Watchdog Timer 6.17 Input/Output configuration module (IOCONFIG) The General Purpose Input/Output (GPIO) pins can be controlled through the register interface provided in the IOCONFIG module. Next to several dedicated GPIO pins, most digital IO pins can also be used as GPIO if they are not required for their normal, dedicated function ...
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... NXP Semiconductors 6.19 Event router The event router extends the interrupt capability of the system by offering a flexible and versatile way of generating interrupts. Combined with the wake-up functionality of the CGU, it also offers a way to wake-up the system from suspend mode (with all clocks deactivated). ...
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... NXP Semiconductors 6.20 Random Number Generator (RNG) The random number generator generates true random numbers for use in advanced security and Digital Rights Management (DRM) related schemes. These schemes rely upon truly random, i.e. completely unpredictable numbers. This module has the following features: • ...
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... NXP Semiconductors The SPI/SSI-bus is a 5-wire interface, and it is suitable for low, medium, and high data rate transfers. This module has the following features: • Supports Motorola SPI frame format with a word size of 8/16 bits. • Texas Instruments SSI (Synchronous Serial Interface) frame format with a word size of 4 bit to 16 bit. • ...
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... NXP Semiconductors – PCM (Pulse Code Modulation): Single clocking physical format. – IOM-2 (Extended ISDN-Oriented modular): Double clocking physical format. • Twelve 8 bit slots in a frame with enabling control per slot. • Internal frame clock generation in master mode. • Receive and transmit DMA handshaking using a request/clear protocol. ...
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... NXP Semiconductors • Fast mode (400 kHz SCL with 24 MHz APB clock; 325 kHz with12 MHz APB clock; 175 kHz with 6 MHz APB clock). • Interrupt support. • Supports DMA transfers (single). • Four modes of operation: – Master transmitter – Master receiver – ...
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... NXP Semiconductors Table 11. Pin descriptions of multiplexed pins Pin name Default signal mLCD_DB_3 LCD_DB_3 mLCD_DB_4 LCD_DB_4 mLCD_DB_5 LCD_DB_5 mLCD_DB_6 LCD_DB_6 mLCD_DB_7 LCD_DB_7 mLCD_DB_8 LCD_DB_8 mLCD_DB_9 LCD_DB_9 mLCD_DB_10 LCD_DB_10 mLCD_DB_11 LCD_DB_11 mLCD_DB_12 LCD_DB_12 mLCD_DB_13 LCD_DB_13 mLCD_DB_14 LCD_DB_14 mLCD_DB_15 LCD_DB_15 Storage related pin multiplexing ...
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... NXP Semiconductors Table 11. Pin descriptions of multiplexed pins Pin name Default signal mLCD_DB_3 LCD_DB_3 mLCD_DB_4 LCD_DB_4 mLCD_DB_5 LCD_DB_5 mLCD_DB_6 LCD_DB_6 mLCD_DB_7 LCD_DB_7 mLCD_DB_8 LCD_DB_8 mLCD_DB_9 LCD_DB_9 mLCD_DB_10 LCD_DB_10 mLCD_DB_11 LCD_DB_11 mLCD_DB_12 LCD_DB_12 mLCD_DB_13 LCD_DB_13 mLCD_DB_14 LCD_DB_14 mLCD_DB_15 LCD_DB_15 Storage related pin multiplexing ...
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... NXP Semiconductors Table 11. Pin descriptions of multiplexed pins Pin name Default signal NAND flash related pin multiplexing mNAND_RYBN0 NAND_RYBN0 mNAND_RYBN1 NAND_RYBN1 mNAND_RYBN2 NAND_RYBN2 mNAND_RYBN3 NAND_RYBN3 Audio related pin multiplexing mI2STX_DATA0 I2STX_DATA0 mI2STX_BCK0 I2STX_BCK0 mI2STX_WS0 I2STX_WS0 mI2STX_CLK0 I2STX_CLK0 UART related pin multiplexing mUART_CTS_N ...
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... NXP Semiconductors control NAND_NCS_[0:3] control NAND_RYBN[0:3] NAND FLASH INTERFACE control EBI_NCAS_BLOUT_0 3 EBI_NRAS_BLOUT_1 EBI_DQM_0_NOE MPMC LCD Fig 9. Diagram of LCD and MPMC multiplexing Figure 9 only shows the signals that are involved in pad-muxing, so not all interface signals are visible. The EBI unit between the NAND flash interface and the MPMC contains an arbiter that determines which interface is muxed to the outside world ...
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... NXP Semiconductors 2. Dedicated LCD interface only: This is the LCD mode. The NAND flash supply voltage (SUP4) can be different from the LCD supply voltage (SUP8). 6.29 Timer module The LPC3152/3154 contains four fully independent timer modules, which can be used to generate interrupts after a pre-set time interval has elapsed. ...
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... NXP Semiconductors • Audio codec on the analog die (see – Class AB amplifier – Stereo Analog-to-Digital Converter (SADC) – analog inputs/outputs – Analog Volume Control (AVC) – Stereo Digital-to-Analog Converter (SDAC) • and I LPC3152/3154 ANALOG DIE/AUDIO CODEC MUX_R0 ADC_VINR MUX_R1 ADC_TINR ADC_MIC ...
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... NXP Semiconductors 2 The I S0/1 module has the following features: • Receive input supports master mode and slave mode. • Transmit output supports master mode. • Supports LSB justified words of 16, 18, 20 and 24 bits. • Supports a configurable number of bit clock periods per word select period (up to 128 bit clock periods). • ...
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... NXP Semiconductors LPC3152/3154 ADC_VINR, ADC_VINL, ADC_MIC, ADC_ TINR, ADC_TINL ADC_VREFP, ADC_VREFN ADC_VREF HP_OUTR, HP_OUTL, HP_OUTC HP_VREF, HP_FCR, HP_FCL DAC_VREFP, DAC_VREFN (digital die (digital die) Fig 11. Block diagram of the analog die 7.2 Audio codec 7.2.1 Stereo Digital-to-Analog Converter (SDAC) The Stereo Digital-to-Analog Converter converts a digital audio signal into an analog audio signal ...
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... NXP Semiconductors • Controlled power down sequence comprising a raised cosine mute function followed ramp down to zero to avoid audible plops or clicks. • Digital dB-linear volume control in 0.25 dB steps. • Digital de-emphasis for 32 kHz, 44.1 kHz, 48 kHz, and 96 kHz. • Selection for the up-sampling filter characteristics (sharp/slow roll-off). ...
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... NXP Semiconductors Fig 12. Stereo ADC for audio This module has the following features: • Three input options: line-in (stereo), tuner-in (stereo), microphone-in (mono). • Low-Noise Amplifier (LNA) with a fixed 30 dB gain for the microphone input. • Programmable Gain Amplifier (PGA). Gain can be set in steps dB. ...
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... NXP Semiconductors • The nominal charge current is programmed with an external program-resistor. This allows the charge current to be adapted to the USB enumeration. • Uses a widespread method to charge a Li-ion battery with the following stages: – Trickle charging with a small current for an (almost) empty battery. ...
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... NXP Semiconductors LPC3152/3154 DIGITAL DIE SUP5 SUP4/8 3.3 V MODE SUP3 PSU_VOUT1 PSU_VOUT2 SUP1 PSU_VOUT3 SUP4/8 1.8 V MODE Fig 13. LPC3152/3154 supply voltages of the analog and digital die This module has the following features: • Takes power from the Li-Ion battery or the USB power supply. ...
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... NXP Semiconductors • Provides ‘Supply_OK’ detection connected to the system reset signal. 7.6 Real-Time Clock (RTC) The Real-Time Clock module keeps track of the actual date and time, also when the system is switched off. Advanced Digital Rights Management (DRM) schemes require a secure and accurate real-time clock for managing rights such as time-limited playback rights ...
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... NXP Semiconductors 8. Limiting values Table 12. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter All digital I/O pins V input voltage i V output voltage o I output current o Temperature values T junction temperature j T storage temperature stg T ambient temperature amb ...
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... NXP Semiconductors Table 13: Static characteristics − ° ° +85 C unless otherwise specified. amb Symbol Parameter V oscillator and PLL DD(OSC_PLL) supply voltage V ADC supply voltage DD(ADC) V polyfuse programming prog(pf) voltage V bus supply voltage BUS V USB analog supply DDA(USB)(3V3) voltage (3 PLL analog supply DDA(PLL)(1V2) voltage (1 ...
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... NXP Semiconductors Table 13: Static characteristics − ° ° +85 C unless otherwise specified. amb Symbol Parameter C input capacitance i Output pins and I/O pins configured as output V output voltage O V HIGH-level output OH voltage V LOW-level output OL voltage I HIGH-level output OH current I LOW-level output OL current I OFF-state output ...
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... NXP Semiconductors Table 13: Static characteristics − ° ° +85 C unless otherwise specified. amb Symbol Parameter 2 I C0-bus pins I OFF-state output OZ current V HIGH-level input IH voltage V LOW-level input IL voltage V hysteresis voltage hys V LOW-level output OL voltage I input leakage current LI USB V common-mode input i(cm) voltage ...
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... NXP Semiconductors [5] The integral non-linearity ( the peak difference between the center of the steps of the actual and the ideal transfer curve after L(adj) appropriate adjustment of gain and offset errors. See [6] The offset error ( the absolute difference between the straight line which fits the actual curve and the straight line which fits the O ideal curve ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 14. ADC characteristics LPC3152_3154 Preliminary data sheet ...
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... NXP Semiconductors Fig 15. Suggested 10-bit ADC interface 9.2 Analog die Table 15. Static characteristics of the analog die supply pins − ° ° +85 C unless otherwise specified. amb Symbol Parameter V input/output supply voltage DD(IO) V core supply voltage DD(CORE) 9.2.1 PSU Table 16: Static characteristics of the PSU − ...
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... NXP Semiconductors Table 16: Static characteristics of the PSU − ° ° +85 C unless otherwise specified. amb Symbol Parameter output PSU_VOUT2 V output voltage O ΔV output voltage deviation o I output current O I maximum LDO load current L(LDO)(max) output PSU_VOUT3 V output voltage O I output current ...
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... NXP Semiconductors Table 17: Static characteristics of the analog input − ° ° +85 C unless otherwise specified. amb Symbol Parameter I ADC analog supply current (3.3 V) DDA(ADC)(3V3) I ADC analog supply current (1.8 V) DDA(ADC)(1V8) I negative reference current ref(neg) I positive reference current ref(pos) I SDC analog supply current ...
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... NXP Semiconductors Table 18. Efficiency of output on PSU_VOUT1 (PSU_VOUT1 programmed to 2. BAT on pin PSU_VBAT 2 2.8 3.598 4.396 5.195 5.994 6.793 7.59 8.388 9.231 13.32 17.368 25.59 9.2.1.2 PSU_VOUT2 efficiency 100 η (%) SUP1 = 1.07 V. SUP2: V SUP3: V PSU_VOUT2 = 1.07 V. Fig 17. Efficiency PSU_VOUT2 LPC3152_3154 Preliminary data sheet ...
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... NXP Semiconductors Table 19. Efficiency of output on PSU_VOUT2 (PSU_VOUT2 programmed to 1. BAT on pin PSU_VBAT 1.002 1.357 1.71 2.063 2.415 2.77 3.122 3.472 3.822 4.172 5.7 7.292 10.466 LPC3152_3154 Preliminary data sheet BAT DD DD for supply domain SUP1 3.602 1 1.072 3.6022 2 1.069 3.6021 3 1.068 3 ...
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... NXP Semiconductors 9.2.2 Li-ion charger Table 20: Static characteristics of the Li-ion charger Symbol Parameter V battery voltage bat I load current load constant-current charge (fast charge) mode I battery current bat trickle charge mode V battery trickle charge threshold th(trch)bat voltage constant-voltage charge mode V battery constant-voltage charge ...
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... NXP Semiconductors 10. Dynamic characteristics 10.1 Digital die 10.1.1 LCD controller 10.1.1.1 Intel 8080 mode Table 21. Dynamic characteristics: LCD controller in Intel 8080 mode pF amb Symbol Parameter t address set-up time su(A) t address hold time h(A) t access cycle time cy(a) t write enable pulse width ...
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... NXP Semiconductors 10.1.1.2 Motorola 6800 mode Table 22. Dynamic characteristics: LCD controller in Motorola 6800 mode pF amb Symbol Parameter t address set-up time su(A) t address hold time h(A) t access cycle time cy(a) t rise time r t fall time f t data input set-up time su(D) t data input hold time ...
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... NXP Semiconductors 10.1.1.3 Serial mode Table 23. Dynamic characteristics: LCD controller serial mode pF amb Symbol Parameter T clock cycle time cy(clk) t HIGH clock pulse width w(clk)H t LOW clock pulse width w(clk)L t rise time r t fall time f t address set-up time su(A) t address hold time ...
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... NXP Semiconductors 10.1.2 SRAM controller Table 24. Dynamic characteristics: static external memory interface − ° ° pF +85 C, unless otherwise specified amb Symbol Parameter Common to read and write cycles t CS LOW to address valid CSLAV time Read cycle parameters t OE LOW to address valid OELAV ...
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... NXP Semiconductors EBI_NSTCS_X t CSLAV EBI_A_[15:0] EBI_DQM_0_NOE t t EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 t EBI_D_[15:0] Fig 21. External memory read access to static memory LPC3152_3154 Preliminary data sheet t OELAV t OELOEH CSLOEL BLSLAV t BLSLBLSH CSLBLSL All information provided in this document is subject to legal disclaimers. Rev. 0.12 — 27 May 2010 LPC3152/3154 ...
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... NXP Semiconductors EBI_NSTCS_X EBI_A_[15:0] EBI_D_[15:0] EBI_NWE EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 Fig 22. External memory write access to static memory 10.1.3 SDRAM controller Table 25. Dynamic characteristics of SDR SDRAM memory interface − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions f operating frequency oper T clock cycle time ...
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... NXP Semiconductors Table 25. Dynamic characteristics of SDR SDRAM memory interface − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions t output hold time on pin EBI_CKE h(o) on pins EBI_NRAS_BLOUT, EBI_NCAS_BLOUT, EBI_NWE, EBI_NDYCS on pins EBI_DQM_1, EBI_DQM_0_NOE t address valid delay d(AV) time t address hold time ...
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... NXP Semiconductors T CLCL t CHCX EBI_CLKOUT EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS EBI_DQMx EBI_A_[15:2] EBI_D_[15:0] EBI_CKE is HIGH. Fig 23. SDRAM burst read timing LPC3152_3154 Preliminary data sheet t CLCX t t d(o) h(o) READ NOP NOP NOP t d(o) t h(A) BANK su(D) h(D) COLUMN DATA n CAS DATA n+1 LATENCY = 2 All information provided in this document is subject to legal disclaimers ...
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T CLCL t CLCX t CHCX EBI_CLKOUT EBI_CKE EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS EBI_DQMx EBI_A_[15:2] EBI_D_[15:0] Fig 24. SDRAM bank activate and write timing t ...
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... NXP Semiconductors 10.2 NAND flash memory controller Table 26. Dynamic characteristics of the NAND Flash memory controller − ° +85 amb Symbol t REH CLS t CLH t ALS t ALH [ NANDFLASH_NAND_CLK, see LPC315x user manual. HCLK [2] See registers NandTiming1 and NandTiming2 in the LPC315x user manual. [3] Each timing parameter can be set from 7 nand_clk clock cycles to 1 nand_clk clock cycle. (A programmed zero value is treated as a one) ...
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... NXP Semiconductors 10.2.1 Crystal oscillator Table 27: Dynamic characteristics: crystal oscillator Symbol Parameter f oscillator frequency osc δ clock duty cycle clk C crystal capacitance xtal t start-up time startup P drive power drive 10.2.2 SPI Table 28. Dynamic characteristics of SPI pins − ° ° +85 C for industrial applications ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 26. SPI master timing (CPHA = 1) Fig 27. SPI master timing (CPHA = 0) LPC3152_3154 Preliminary data sheet t SPICLK t SPISEDV DATA VALID MOSI MISO DATA VALID t SPICLK SCK (CPOL = 0) SCK (CPOL = 1) t SPISEDV DATA VALID MOSI t DATA VALID MISO All information provided in this document is subject to legal disclaimers. Rev. 0.12 — ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 28. SPI slave timing (CPHA = 1) Fig 29. SPI slave timing (CPHA = 0) 10.2.2.1 Texas Instruments synchronous serial mode (SSP mode) Table 29. Dynamic characteristic: SPI interface (SSP mode) − ° ° + (SUP3) over specified ranges. amb DD(IO) Symbol ...
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... NXP Semiconductors shifting edges SCK MOSI MISO Fig 30. MISO line set-up time in SSP Master mode LPC3152_3154 Preliminary data sheet t su(SPI_MISO) All information provided in this document is subject to legal disclaimers. Rev. 0.12 — 27 May 2010 LPC3152/3154 sampling edges 002aad326 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 2 10.2.3 I S-interface Table 30. Dynamic characteristics: I − ° ° +85 C for industrial applications amb Symbol Parameter common to input and output T clock cycle time cy(clk) t fall time f t rise time r output t pulse width HIGH WH t pulse width LOW WL t data output valid time ...
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... NXP Semiconductors I2SRX_SCK I2SRX_SDA I2SRX_WS 2 Fig 32. I S-bus timing (input) 2 10.2.4 I C-bus Table 31. Dynamic characteristic: I − ° ° [ +85 C. amb Symbol Parameter f SCL clock frequency SCL t output fall time f(o) t rise time r t fall time f t bus free time between a STOP and ...
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... NXP Semiconductors SDA t t BUF LOW SCL HD;STA Remark: Signals SDA and SCL correspond to pins I2C_SDAx and I2C_SCLx ( 1). 2 Fig 33. I C-bus pins clock timing LPC3152_3154 Preliminary data sheet HD;STA HIGH SU;DAT SU;STA All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 10.2.5 USB interface Table 32. Dynamic characteristics: USB pins (high-speed) Ω pF 1 DD(IO) Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT t source jitter for differential transition ...
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... NXP Semiconductors 10.3 Analog die/audio system Table 34. Dynamic characteristics of Class AB amplifier − ° ° +85 C unless otherwise specified. V amb Symbol Parameter V output voltage o P output power o (THD+N)/S Total harmonic distortion plus noise-to-signal ratio S/N Signal-to-noise ratio PSRR power supply ripple rejection α ...
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Application information Table 36. LCD panel connections TFBGA pin # Pin name R8 mLCD_CSB/EBI_NSTCS_0 P7 mLCD_E_RD/EBI_CKE R7 mLCD_RS/EBI_NDYCS T8 mLCD_RW_WR/EBI_DQM_1 T7 mLCD_DB_0/EBI_CLKOUT P8 mLCD_DB_1/EBI_NSTCS_1 ...
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... NXP Semiconductors 12. Marking Table 37. LPC3152/3154 Marking Line A LPC3152_3154 Preliminary data sheet Marking Description LPC3152/3154 BASIC_TYPE All information provided in this document is subject to legal disclaimers. Rev. 0.12 — 27 May 2010 LPC3152/3154 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 13. Package outline TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 0.7 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.35 0.80 0.45 12.1 mm 1.15 0.25 0.65 0.35 11.9 OUTLINE VERSION IEC SOT930-1 Fig 35 ...
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... NXP Semiconductors 14. Abbreviations Table 38: Abbreviations Acronym ADC ADC10B AES AVC BIU CBC CD CGU DFU DMA DRM ECC FIR HP IOCONFIG ROM IrDA JTAG ISRAM JTAG LCD LDO LNA MMU NTC OTP PCM PGA PHY PLL PSU PWM RNG SDC SHA1 SIR SPI ...
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... NXP Semiconductors Table 38: Abbreviations Acronym Timer UART USB 2.0 HS OTG Universal Serial Bus 2.0 High-Speed On-The-Go LPC3152_3154 Preliminary data sheet …continued Description Timer module Universal Asynchronous Receiver Transmitter All information provided in this document is subject to legal disclaimers. Rev. 0.12 — 27 May 2010 LPC3152/3154 © ...
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... NXP Semiconductors 15. Revision history Table 39: Revision history Document ID Release date LPC3152_3154 v.0.12 <tbd> • Modifications: Reset state of JTAG pins and GPIO0, GPIO1, and GPIO2 pins updated in • Document template updated. • Digital I/O level for pin CLOCK_OUT corrected in • USB Hi-speed logo added. ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . 16 6.1 ARM926EJ 6.2 Memory map 6.2.1 Analog die memory organization . . . . . . . . . . 17 6.3 JTAG ...
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... NXP Semiconductors 16 Legal information 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 85 16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 16.4 Trademarks Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 LPC3152/3154 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. ...