TEF6606T/V5,512 NXP Semiconductors, TEF6606T/V5,512 Datasheet - Page 28

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TEF6606T/V5,512

Manufacturer Part Number
TEF6606T/V5,512
Description
IC TUNER CAR RADIO AM/FM 32SOIC
Manufacturer
NXP Semiconductors
Datasheet

Specifications of TEF6606T/V5,512

Modulation Or Protocol
AM, FM
Applications
AM/FM Radio Receiver
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Voltage - Supply
8.5V
Package / Case
32-SOIC (0.300", 7.50mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Frequency
-
Operating Temperature
-
Sensitivity
-
Memory Size
-
Data Rate - Maximum
-
Current - Receiving
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
935288263512
NXP Semiconductors
LPC3152_3154
Preliminary data sheet
Fig 6. CGU block diagram
EXTERNAL
CRYSTAL
I2SRX_BCK0
I2SRX_WS0
The LPC3152/3154 has 11 clock domains (n = 11). The number of fractional dividers depends on the clock domain.
clock resources
6.16 Watchdog Timer (WDT)
OSCILLATOR
The Watchdog Timer can be used to generate a system reset if there is a CPU/software
crash. In addition the watchdog timer can be used as an ordinary timer.
how the Watchdog Timer module is connected in the system.
This module has the following features:
Based on the input of the Watchdog timer (see also
generate a system-wide reset in the case of a system stall.
In the event of a software or hardware failure, generates a chip-wide reset request
when its programmed time-out period has expired (output m1).
Watchdog counter can be reset by a periodical software trigger.
After a reset, a register will indicate whether a reset has occurred because of a
watchdog generated reset.
Watchdog timer can also be used as a normal timer in addition to the watchdog
functionality (output m0).
All information provided in this document is subject to legal disclaimers.
Rev. 0.12 — 27 May 2010
I
2
SYSTEM
S/AUDIO
PLL
PLL
SWITCHBOX
CLOCK DOMAIN 0
CLOCK DOMAIN n
BASE
BASE
subdomain clocks
Section
FRACTIONAL
FRACTIONAL
FRACTIONAL
FRACTIONAL
LPC3152/3154
DIVIDER 0
DIVIDER 6
DIVIDER i
DIVIDER j
6.16), the CGU can
© NXP B.V. 2010. All rights reserved.
Figure 7
clock outputs
002aae385
to modules
shows
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