MC33596FCER2 Freescale Semiconductor, MC33596FCER2 Datasheet - Page 18

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MC33596FCER2

Manufacturer Part Number
MC33596FCER2
Description
IC RX UHF PLL TUNED 32-QFN
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC33596FCER2

Frequency
304, 315, 426, 434, 868 & 915MHz
Sensitivity
-104dBm
Data Rate - Maximum
22.4 kBaud
Modulation Or Protocol
FSK, OOK
Applications
General Data Transfer
Current - Receiving
10.3mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Voltage - Supply
2.7 V ~ 3.6 V, 4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Memory Size
-
Receive Mode
For all states: At any time, a low level applied to STROBE forces the circuit to state 10, and a low level
applied on CONFB forces the state machine to state 1, configuration mode.
When an EOM occurs before the current byte is fully shifted out, dummy bits are inserted until the number
of shifted bits is a multiple of 8.
18
State 10:
The receiver is off, but the strobe oscillator and the off counter are running. Forcing STROBE pin
to the low level maintains the system in this state.
State 11:
The receiver is waiting for a valid ID. If an ID, or its complement, is detected, the state machine
advances to state 12; otherwise, the circuit goes back to state 10 at the end of the RON time, if
STROBE ≠ 1.
State 12:
An ID or its complement has been detected. The data manager is now waiting for a header or its
complement. If neither a header, nor its complement, has been received before a time-out of 256
bits at data rate, the system returns to state 10.
State 13:
A header, or its complement, has been received. Data and clock signals are output on the SPI port
until EOM indicates the end of the data sequence. If the complement of the header has been
received, output data are complemented also.
MC33596 Data Sheet, Rev. 4
Freescale Semiconductor

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