MC33596FCER2 Freescale Semiconductor, MC33596FCER2 Datasheet - Page 24

• Manufacturer Part Number: MC33596FCER2
• Description: IC RX UHF PLL TUNED 32-QFN
• Manufacturer: Freescale Semiconductor

Specifications of MC33596FCER2

• Frequency: 304, 315, 426, 434, 868 & 915MHz
• Sensitivity: -104dBm
• Data Rate - Maximum: 22.4 kBaud
• Modulation Or Protocol: FSK, OOK
• Applications: General Data Transfer
• Current - Receiving: 10.3mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.7 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -

Receive Mode
11.4.2 Operation
Two modes of operation are available: sample mode and continuous mode.
11.4.2.1 Sample Mode
Sample mode allows the peak power of a specific pulse in an incoming frame to be measured.
The quasi peak detector is reset by closing S1. After 7 × T
is set high. On the falling edge of RSSIC, S2 is opened. The voltage on RSSIOUT is sampled and held.
The last RSSI conversion results are stored in the RSSI register and no further conversion is done.
The RSSI register is updated every 32 × T
RSSIC is 32 × T
11.4.2.2 Continuous Mode
Continuous mode is used to make a peak measurement on an incoming frame, without having to select a
specific pulse to be measured.
The quasi peak detector is reset by closing S1. After 7 × T
is set high. As long as RSSIC is kept high, S2 is closed, and RSSIOUT follows the peak value with a decay
time constant of 5 ms.
The ADC runs continuously, and continually updates the RSSI register. Thus, reading this register gives
the most recent conversion value, prior to the register being read. The minimum duration of the high pulse
on CONFB is 32 × T
24
RSSI Register
RSSIOUT
CONFB
RSSIC
MOSI
MISO
S1
S2
digclk
Frozen
Open
Peak Detector
Closed
digclk
.
Reset
7 x t
.
digclk
Updated
Figure 16. RSSI Operation in Sample Mode
Closed
Open
Sampling
MC33596 Data Sheet, Rev. 4
digclk
. Therefore, the minimum duration of the high pulse on
digclk
CMD
digclk
Sampled and Hold RSSI Voltage
, S1 is released. S2 is closed when RSSIC
, S1 is opened. S2 is closed when RSSIC
RSSI Value
Closed
Frozen
Open
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