SI4322-A1-FT Silicon Laboratories Inc, SI4322-A1-FT Datasheet - Page 21

• Manufacturer Part Number: SI4322-A1-FT
• Description: IC RCVR FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: FSK Receiverr

Specifications of SI4322-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 868MHz, 915MHz
• Sensitivity: -104dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.2 V ~ 3.8 V
• Operating Frequency: 915 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 12 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1628-5

5.10. Low Battery Detector and Microcontroller Clock Divider Command
Bit 7:5 <cd2 : cd0>:Clock divider configuration (valid only if the crystal oscillator is on):
Bit 4 <elfc>:
Bit 3:0 <t3 : t0>: The 4-bit value T of <t3 : t0> determines the threshold voltage of the threshold voltage V
5.11. AFC Command
Bit 0 <aen>:
Bit 1 <oe>:
Bit 2 <fi>:
Bit 3 <st>:
Bit 5:4 <rl1 : rl0>: Limit the value of the frequency offset register to the following values:
Bit
Bit
15
15
1
1
14
14
1
1
Enables the low frequency (32 kHz) clock during sleep mode. The clock signal is present on the
CLK pin regardless to the state of the dc bit (
detector:
Enables the calculation of the offset frequency by the AFC circuit (it allows the addition of the
content of the output register to the frequency control word of the PLL).
Enables the output (frequency offset) register
Switches the circuit to high accuracy (fine) mode. In this case the processing time is about four
times longer, but the measurement uncertainty is less than half.
Strobe edge. When st goes to high, the actual latest calculated frequency error is stored into the
output registers of the AFC block.
13
13
0
0
V
lb
12
12
0
= 2.0 V + T x 0.1 V
0
11
11
0
0
10
10
1
0
cd2 cd1 cd0
0
0
0
0
1
1
1
1
rl1
9
1
9
1
0
0
1
1
0
0
1
1
0
0
1
1
rl0
8
0
0
1
0
1
8
0
0
1
0
1
0
1
0
1
cd2 cd1 cd0 elfc
Rev. 1.2
a1
7
7
Max dev [f
No restriction
Frequency [MHz]
a0
Clock Output
6
6
±4
±2
±1
"5.3. Configuration Setting Command" on page 16
1.25
1.66
3.33
rl1
2.5
10
5
1
2
5
5
res
]
rl0
4
4
st
3
t3
3
t2
2
fi
2
oe aen
t1
1
1
t0
0
0
Si4322
C213h
C687h
POR
POR
lb
).
of the
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