SI4322-A1-FT Silicon Laboratories Inc, SI4322-A1-FT Datasheet - Page 31

• Manufacturer Part Number: SI4322-A1-FT
• Description: IC RCVR FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: FSK Receiverr

Specifications of SI4322-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 868MHz, 915MHz
• Sensitivity: -104dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.2 V ~ 3.8 V
• Operating Frequency: 915 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 12 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1628-5

The clock switching synchronization circuit detects the falling edges of the clocks. One consequence is a latency of
0 to T
beginning of the intermediate length (T
change to occur. Changing from fast to slow clock, it is automatically ensured by entering into the sleep mode if the
elfc bit is enabled. As the crystal oscillator is normally stopped while the slow clock is used, when changing back to
fast clock the crystal oscillator startup time has to pass first before the above mentioned latency period starts. The
startup condition is detected internally, so no software timing is necessary.
10. Wake-Up Timer Calibration
By default, the wake-up timer is calibrated every time it is enabled by setting the et bit in the "5.3. Configuration
Setting Command" on page 16. After timeout the timer restarts automatically and can be stopped by resetting the
et bit. If the timer is programmed to run for longer periods, at approximately every 30 seconds it performs additional
self-calibration.
This feature can be disabled to avoid sudden changes in the actual wake-up time period. A suitable software
algorithm can then compensate for the gradual shift caused by temperature change.
Bit dcal in the "5.15. Extended Features Command" on page 26 controls the automatic calibration feature. It is
reset to 0 at power-on and the automatic calibration is enabled. This is necessary to compensate for process
tolerances. After one calibration cycle further (re)calibration can be disabled by setting this bit to 1.
11. RX-TX Alignment Procedures
RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these
errors it is suggested to use the same crystal type and the same PCB layout for the crystal placement on the RX
and TX PCBs.
To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of
accuracy. Do not measure the output at the XTL pin since the measurement process itself will change the
reference frequency. Since the carrier frequencies are derived from the reference frequency, having identical
reference frequencies and nominal frequency settings at the TX and RX side there should be no offset if the CLK
signals have identical frequencies.
It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the
receiver. By reading out the status byte from the receiver, the actual measured offset frequency will be reported. In
order to get accurate values the AFC has to be disabled during the read by clearing the aen bit in the "5.11. AFC
Command" on page 21.
slow
+ T
slow clock
fast
fast clock
output
from the occurrence of a clock change request (entering into sleep mode or interrupt) until the
0.5 · T
fast
< T
x
< 0.5 · T
x
) half cycle. The other is that both clocks should be up and running for the
slow
T
slow
T
Rev. 1.2
x
T
clock periods are not to scale
fast
Si4322
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