AT86RF212-ZU Atmel, AT86RF212-ZU Datasheet - Page 105

• Manufacturer Part Number: AT86RF212-ZU
• Description: IC TXRX ZIGBE/802.15.4/ISM 32QFN
• Manufacturer: Atmel

Specifications of AT86RF212-ZU

• Frequency: 700MHz, 800MHz, 900MHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, ISM
• Applications: ISM, ZigBee™
• Power - Output: 10dBm
• Sensitivity: -110dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 9.2mA
• Current - Transmitting: 25mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 769 MHz to 935 MHz
• Interface Type: SPI
• Noise Figure: 7 dB
• Output Power: 21 dB
• Operating Supply Voltage: 1.8 V, 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 25 mA
• Minimum Operating Temperature: - 40 C
• Modulation: OQPSK
• Protocol Supported: 802.15.4
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.3.6 Register Description
8168C-MCU Wireless-02/10
Register 0x16 (RF_CTRL_0):
This register contains control signals to configure the transmit path.
Table 7-10. Register 0x16 (RF_CTRL_0)
• Bit 7:6 – PA_LT
These register bits control the lead time of the PA enable signal relative to the TX data
start, see Figure 7-9. This allows to enable the PA 2, 4, 6, or 8 µs before the transmit
signal starts. The PA enable signal can also be output at pin DIG3/DIG4 to provide a
control signal for an external RF front-end; for details, refer to section 9.4.
Table 7-11. PA Enable Time Relative to the TX start
Setting of PA_LT is only effective in TRX_OFF, PLL_ON, and TX_ARET_ON mode.
• Bit 5:2 – Reserved
• Bit 1:0 – GC_TX_OFFS
These register bits provide an offset between the TX power control word TX_PWR
(register 0x05, PHY_TX_PWR) and the actual TX power. This 2-bit word is added to the
TX power control word before it is applied to the circuit block which adjusts the TX
power. It can be used to compensate differences of the average TX power depending of
the modulation format, see Table 7-16 .
Table 7-12. TX Power Offset
Register 0x05 (PHY_TX_PWR):
This register controls the transmitter output power.
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
Register Bits
PA_LT
Register Bits
GC_TX_OFFS
7
PA_LT[1]
R/W
0
3
Reserved
R
0
Value
Value
0
1
2
3
0
1
2
3
6
PA_LT[0]
R/W
0
2
Reserved
R
0
PA Enable Lead Time [μs]
5
Reserved
R/W
1
1
GC_TX_OFFS[1]
R/W
0
TX Power Offset [dB]
+1
+2
2
4
6
8
-1
0
AT86RF212
4
Reserved
R/W
1
0
GC_TX_OFFS[0]
R/W
1
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