AT86RF212-ZU Atmel, AT86RF212-ZU Datasheet - Page 35

• Manufacturer Part Number: AT86RF212-ZU
• Description: IC TXRX ZIGBE/802.15.4/ISM 32QFN
• Manufacturer: Atmel

Specifications of AT86RF212-ZU

• Frequency: 700MHz, 800MHz, 900MHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, ISM
• Applications: ISM, ZigBee™
• Power - Output: 10dBm
• Sensitivity: -110dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 9.2mA
• Current - Transmitting: 25mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 769 MHz to 935 MHz
• Interface Type: SPI
• Noise Figure: 7 dB
• Output Power: 21 dB
• Operating Supply Voltage: 1.8 V, 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 25 mA
• Minimum Operating Temperature: - 40 C
• Modulation: OQPSK
• Protocol Supported: 802.15.4
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.1.3 Interrupt Handling
Figure 5-2. Timing of RX_START, AMI, and TRX_END Interrupts in Basic Operating Mode for O-QPSK 250 kbit/s Mode
5.1.4 Timing
8168C-MCU Wireless-02/10
State
SLP_TR
IRQ
Processing Delay
Number of Octets
Frame Content
State
IRQ
Interrupt latency
PLL_ON
-t
TR10
0
t
TR10
(parameter 10.4.12). During reset, the microcontroller has to set the radio transceiver
control pins SLP_TR and /SEL to their default values.
An overview of the register reset values is provided in Table 11-2.
All interrupts provided by the AT86RF212 (see Table 4-15) are supported in Basic
Operating Mode. For example, interrupts are provided to observe the status of radio
transceiver RX and TX operations.
When being in receive mode, IRQ_2 (RX_START) indicates the detection of a non-zero
PHR first, IRQ_5 (AMI) an address match, and IRQ_3 (TRX_END) the completion of
the frame reception. During transmission, IRQ_3 (TRX_END) indicates the completion
of the frame transmission.
Figure 5-2 shows an example for a transmit/receive transaction between two devices
and the related interrupt events in Basic Operating Mode. Device 1 transmits a frame
containing a MAC header, MAC payload, and a valid FCS. The end of the frame
transmission is indicated by IRQ_3 (TRX_END).
The frame is received by Device 2. Interrupt IRQ_2 (RX_START) indicates the
detection of a valid PHR field and IRQ_3 (TRX_END) the completion of the frame
reception. If the frame passes the Frame Filter (refer to 6.2), an address match interrupt
IRQ_5 (AMI) is issued after the reception of the MAC header (MHR).
Processing delay t
The following paragraphs depict state transitions and their timing properties. Timings
are explained in Table 5-1 and section 10.4.
RX_ON
Preamble
4
128
IRQ
SFD
is a typical value, refer to section 10.4.
1
160
PHR
1
BUSY_TX
192
IRQ_2 (RX_START)
t
IRQ
MHR
m
BUSY_RX
IRQ_5 (AMI)
t
IRQ
MSDU
n
IRQ_3 (TRX_END)
192+(m+n+2) 32
FCS
AT86RF212
2
PLL_ON
RX_ON
TRX_END
t
IRQ
Time [μs]
35