AT86RF230-ZUR Atmel, AT86RF230-ZUR Datasheet - Page 69
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AT86RF230-ZUR
Manufacturer Part Number
AT86RF230-ZUR
Description
TXRX LOW POWER 2.4GHZ 32VQFN
Manufacturer
Atmel
Datasheet
1.AT86RF230-ZU.pdf
(98 pages)
Specifications of AT86RF230-ZUR
Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
Applications
Industrial Monitoring and Control, Wireless Alarm and Security Systems
Power - Output
-17dBm ~ 3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
15.5mA
Current - Transmitting
16.5mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
2405 MHz to 2480 MHz
Interface Type
SPI
Noise Figure
6 dB
Output Power
20 dB
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
16.5 mA
Minimum Operating Temperature
- 40 C
Modulation
OQPSK
Protocol Supported
802.15.4
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
1.8V
Operating Supply Voltage (typ)
3V
Operating Supply Voltage (max)
3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Data Rate - Maximum
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT86RF230-ZUR
Manufacturer:
ATMEL
Quantity:
1 000
9.6.5 Register Description
5131E-MCU Wireless-02/09
Bit
0x03
Read/Write
Reset value
Bit
0x03
Read/Write
Reset value
To reduce power consumption and spurious emissions, it is recommended to turn off
the CLKM clock when not in use or to reduce its driver strength to a minimum, refer to
section 4.3.
Note:
During reset procedure, see section 7.1.4.2, register bits CLKM_CTRL are shadowed.
Although the clock setting of CLKM remains after reset, a read access to register bits
CLKM_CTRL delivers the reset value 1. For that reason it is recommended to write the
previous configuration (before reset) to the CLKM_CTRL to align the radio transceiver
behavior and register configuration. Otherwise the CLKM clock rate is set back to the
reset value (1 MHz) after the next SLEEP cycle.
For example if the CLKM clock rate is configured to 16 MHz the CLKM rate remains at
16 MHz after a reset, however the register bits CLKM_CTRL are set back to 1. Since
CLKM_SHA_SEL reset value is 1, the CLKM clock rate would change to 1 MHz after
the next SLEEP cycle if the CLKM_CTRL setting is not updated.
Register 0x03 (TRX_CTRL_0)
The TRX_CTRL_0 register controls the drive current of the digital output pads and the
CLKM clock rate.
• Bit [7:6] – PAD_IO
Refer to in section 4.3.3.
• Bit [5:6] – PAD_IO_CLKM
The register bits PAD_IO_CLKM set the output driver current of pin CLKM.
Table 9-9. CLKM Driver Strength
• Bit 3 – CLKM_SHA_SEL
The register bit CLKM_SHA_SEL defines the commencement of the CLKM clock rate
modifications when changing register bits CLKM_CTRL.
Table 9-10. Commencement of CLKM Clock Rate Modification
Register Bit
PAD_IO_CLKM
Register Bit
CLKM_SHA_SEL
CLKM_SHA_SEL
R/W
R/W
7
0
3
1
PAD_IO
Value
Value
0
1
2
3
0
R/W
R/W
6
0
2
0
Description
2 mA
4 mA
6 mA
8 mA
Description
CLKM clock rate changes immediately
CLKM_CTRL
R/W
R/W
5
0
1
0
PAD_IO_CLKM
R/W
R/W
AT86RF230
4
1
0
1
TRX_CTRL_0
TRX_CTRL_0
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