ATMEGA128RFA1-ZUR Atmel, ATMEGA128RFA1-ZUR Datasheet - Page 337
ATMEGA128RFA1-ZUR
Manufacturer Part Number
ATMEGA128RFA1-ZUR
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
Specifications of ATMEGA128RFA1-ZUR
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
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22.4 Register Description
22.4.1 SPCR – SPI Control Register
8266B-MCU Wireless-03/11
• Bit 7 – SPIE - SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set
and the if the Global Interrupt Enable bit in SREG is set.s
• Bit 6 – SPE - SPI Enable
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any
SPI operations.
• Bit 5 – DORD - Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR - Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when
written logic zero. If the Slave Select pin is configured as an input and is driven low
while MSTR is set, MSTR will be cleared and SPIF in SPSR are set. The user will then
have to set MSTR to re-enable SPI Master mode.
• Bit 3 – CPOL - Clock polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero,
SCK is low when idle. Refer to the "Data Modes" section for an example. The CPOL
functionality is summarized below.
Table 22-3 CPOL Register Bits
• Bit 2 – CPHA - Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading
(first) or trailing (last) edge of SCK. Refer to the "Data Modes" section for an example.
The CPOL functionality is summarized below.
Table 22-4 CPHA Register Bits
• Bit 1:0 – SPR1:0 - SPI Clock Rate Select 1 and 0
Bit
$2C ($4C)
Read/Write
Initial Value
Register Bits
CPOL
Register Bits
CPHA
SPIE
RW
7
0
SPE
RW
6
0
DORD
RW
5
0
Value
Value
0
1
0
1
MSTR
RW
4
0
Description
Rising (Leading Edge), Falling (Trailing
Edge)
Falling (Leading Egde), Rising (Trailing
Edge)
Description
Sample (Leading Edge), Setup (Trailing
Edge)
Setup (Leading Edge), Sample (Trailing
Edge)
CPOL
RW
3
0
ATmega128RFA1
CPHA
RW
2
0
SPR1
RW
1
0
SPR0
RW
0
0
SPCR
337
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