ATMEGA128RFA1-ZUR Atmel, ATMEGA128RFA1-ZUR Datasheet - Page 419
ATMEGA128RFA1-ZUR
Manufacturer Part Number
ATMEGA128RFA1-ZUR
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
Specifications of ATMEGA128RFA1-ZUR
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
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27.6.2 ADC Input Channels
8266B-MCU Wireless-03/11
The ADC input channels can be changed while the ADC is running under the condition
that the previous channel was a single-ended one. Changing between differential
channels however requires that the ADC is disabled and enabled again to make the
ADC go through the initial start-up phase.
If changing from single-ended to single-ended or from single-ended to differential input
channels a settling phase is automatically inserted by the ADC interface logic after the
input channel is modified. The settling phase is required by the ADC and the gain
amplifier to stabilize. If a conversions start is requested during this settling phase, by
setting ADSC or by a trigger event in Auto Triggered mode then the conversion is
started only after the settling phase has completed.
In case the MUXn bits are altered during an ongoing conversion, the ADC input channel
is changed after the conversion has completed. MUXn changes occurring during the
tracking phase, which follows a conversion, will stop the tracking phase and the ADC
settling phase will be entered.
In Free Running mode MUXn can also be modified. In this case the ADC input channel
is changed after the conversion end or from the subsequent tracking phase. As a
consequence the time from one conversion to the next is extended by the duration of
the ADC settling phase.
The ADC settling time t
configuration of the ADSUT and ADTHT bits as shown in
a synchronization delay t
changing the ADC input channel selection and the beginning of the settling phase. For
details see the timing diagrams
Table 27-6. Settling Time after Channel Changes
Figure 27-9. ADC Timing Diagram, Changing MUXn after a Conversion
A D C C lo c k
M U X 5 :0
M U X 5 :0
A D IF
A D C H
A D C L
Channel Transition
Single-Ended to Single-Ended
Differential to Single-Ended
Differential to Differential
Single-Ended to Differential
C o n v e rs io n
C o m p le te
in te rn a l
C o n v e rs io n
S ig n a n d M S B o f R e s u lt
L S B o f R e s u lt
ASET
CHDLY
O ld C h a n n e l
depends on the previous and the new channel and on the
from 2 CPU to 2 ADC Clock cycles is required between
Figure 27-9 below
O ld C h a n n e l
t
C H D L Y
Settling Time t
ADTHT+2
ADTHT+2
Requires the ADC to be disabled and enabled
again.
N e w C h a n n e l
A D C S e ttlin g
N e w C h a n n e l
and
t
A S E T
ATmega128RFA1
A D C In p u t
C h a n n e l is
c h a n g e d
Figure 27-10 on
Table 27-6
ASET
in ADC Clock Cycles
below. Additionally
N e w C o n v e rs io n
c a n b e s ta rte d
fro m h e re
page 420.
419
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