SI1012-A-GM Silicon Laboratories Inc, SI1012-A-GM Datasheet - Page 263
![IC TXRX MCU + EZRADIOPRO](/photos/14/21/142131/42-qfn-series_sml.jpg)
SI1012-A-GM
Manufacturer Part Number
SI1012-A-GM
Description
IC TXRX MCU + EZRADIOPRO
Manufacturer
Silicon Laboratories Inc
Specifications of SI1012-A-GM
Package / Case
42-QFN
Frequency
240MHz ~ 960MHz
Data Rate - Maximum
256kbps
Modulation Or Protocol
FSK, GFSK, OOK
Applications
General Purpose
Power - Output
13dBm
Sensitivity
-121dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
18.5mA
Current - Transmitting
30mA
Data Interface
PCB, Surface Mount
Memory Size
16kB Flash, 768B RAM
Antenna Connector
PCB, Surface Mount
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
240 MHz to 960 MHz
Interface Type
UART, SMBus, SPI, PCA
Output Power
13 dBm
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
4 mA
Minimum Operating Temperature
- 40 C
Modulation
FSK, GFSK, OOK
Protocol Supported
C2, SMBus
Core
8051
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
768 B
Supply Current (max)
4 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1871-5
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Manufacturer
Quantity
Price
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Part Number:
SI1012-A-GMR
Manufacturer:
ROHM
Quantity:
12 000
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determined by the Automatic Packet Handler (if enabled), in conjunction with a variety of Packet Handler
Registers (see Table 23.4 on page 275). If the Automatic Packet Handler is disabled, the entire desired
packet structure should be loaded into FIFO memory; no other fields (such as Preamble or Sync word are
automatically added to the bytes stored in FIFO memory). For further information on the configuration of
the FIFOs for a specific application or packet size, see “Data Handling and Packet Handler” on page 271.
In RX mode, only the bytes of the received packet structure that are considered to be "data bytes" are
stored in FIFO memory. Which bytes of the received packet are considered "data bytes" is determined by
the Automatic Packet Handler (if enabled), in conjunction with the Packet Handler Registers (see
Table 23.4 on page 275). If the Automatic Packet Handler is disabled, all bytes following the Sync word are
considered data bytes and are stored in FIFO memory. Thus, even if Automatic Packet Handling operation
is not desired, the preamble detection threshold and Sync word still need to be programmed so that the RX
Modem knows when to start filling data into the FIFO. When the FIFO is being used in RX mode, all of the
received data may still be observed directly (in real-time) by properly programming a GPIO pin as the
RXDATA output pin; this can be quite useful during application development.
When in FIFO mode, the chip will automatically exit the TX or RX State when either the ipksent or ipkvalid
interrupt occurs. The chip will return to the IDLE mode state programmed in "Register 07h. Operating
Mode and Function Control 1". For example, the chip may be placed into TX mode by setting the txon bit,
but with the pllon bit additionally set. The chip will transmit all of the contents of the FIFO and the ipksent
interrupt will occur. When this interrupt event occurs, the chip will clear the txon bit and return to TUNE
mode, as indicated by the set state of the pllon bit. If no other bits are additionally set in register 07h
(besides txon initially), then the chip will return to the STANDBY state.
In RX mode, the rxon bit will be cleared if ipkvalid occurs and the rxmpk bit (RX Multi-Packet bit, SPI Reg-
ister 08h bit [4]) is not set. When the rxmpk bit is set, the part will not exit the RX state after successfully
receiving a packet, but will remain in RX mode. The microcontroller will need to decide on the appropriate
subsequent action, depending upon information such as an interrupt generated by CRC, packet valid, or
preamble detect.
23.4.2.2. Direct Mode
For legacy systems that perform packet handling within an MCU or other baseband chip, it may not be
desirable to use the FIFO. For this scenario, a Direct Mode is provided which bypasses the FIFOs entirely.
In TX direct mode, the TX modulation data is applied to an input pin of the chip and processed in "real
time" (i.e., not stored in a register for transmission at a later time). A variety of pins may be configured for
use as the TX Data input function.
Furthermore, an additional pin may be required for a TX Clock output function if GFSK modulation is
desired (only the TX Data input pin is required for FSK). Two options for the source of the TX Data are
available in the dtmod[1:0] field, and various configurations for the source of the TX Data Clock may be
selected through the trclk[1:0] field.
The eninv bit in SPI Register 71h will invert the TX Data; this is most likely useful for diagnostic and testing
purposes.
In RX direct mode, the RX Data and RX Clock can be programmed for direct (real-time) output to GPIO
pins. The microcontroller may then process the RX data without using the FIFO or packet handler functions
trclk[1:0]
00
01
10
11
TX/RX Data Clock is available via GPIO (GPIO needs programming accordingly as well)
TX/RX Data Clock is available via the nIRQ pin
No TX Clock (only for FSK)
TX/RX Data Clock is available via SDO pin (only when nSEL is high)
TX/RX Data Clock Configuration
Rev. 1.0
Si1010/1/2/3/4/5
263
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