SI1012-A-GM Silicon Laboratories Inc, SI1012-A-GM Datasheet - Page 370
![IC TXRX MCU + EZRADIOPRO](/photos/14/21/142131/42-qfn-series_sml.jpg)
SI1012-A-GM
Manufacturer Part Number
SI1012-A-GM
Description
IC TXRX MCU + EZRADIOPRO
Manufacturer
Silicon Laboratories Inc
Specifications of SI1012-A-GM
Package / Case
42-QFN
Frequency
240MHz ~ 960MHz
Data Rate - Maximum
256kbps
Modulation Or Protocol
FSK, GFSK, OOK
Applications
General Purpose
Power - Output
13dBm
Sensitivity
-121dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
18.5mA
Current - Transmitting
30mA
Data Interface
PCB, Surface Mount
Memory Size
16kB Flash, 768B RAM
Antenna Connector
PCB, Surface Mount
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
240 MHz to 960 MHz
Interface Type
UART, SMBus, SPI, PCA
Output Power
13 dBm
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
4 mA
Minimum Operating Temperature
- 40 C
Modulation
FSK, GFSK, OOK
Protocol Supported
C2, SMBus
Core
8051
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
768 B
Supply Current (max)
4 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1871-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI1012-A-GMR
Manufacturer:
ROHM
Quantity:
12 000
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Si1010/1/2/3/4/5
28.4. Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA Module 5. The WDT is used
to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified
limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 5 operates as a watchdog timer (WDT). The
Module 5 high byte is compared to the PCA counter high byte; the Module 5 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset
shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and
optionally re-configured and re-enabled if it is used in the system).
28.4.1. Watchdog Timer Operation
While the WDT is enabled:
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but
user software has not enabled the PCA counter. If a match occurs between PCA0CPH5 and PCA0H while
the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a
write of any value to PCA0CPH5. Upon a PCA0CPH5 write, PCA0H plus the offset held in PCA0CPL5 is
loaded into PCA0CPH5 (See Figure 28.11).
370
PCA0CPLn
PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2 – CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 5 is forced into software timer mode.
Writes to the Module 5 mode register (PCA0CPM5) are disabled.
Write to
Reset
PCA0CPHn
Write to
0
1
ENB
ENB
W
M
P
1
6
n
1
O
M
E
C
n
PCA0CPMn
C
A
P
P
n
0 0 x 0
C
N
A
P
n
M
A
T
n
PCA Timebase
O
G
T
n
W
M
P
n
E
C
C
F
n
x
Figure 28.10. PCA 16-Bit PWM Mode
Enable
PCA0CPHn
PCA0H
16-bit Comparator
Rev. 1.0
PCA0CPLn
PCA0L
Overflow
match
S
R
CLR
SET
Q
Q
CEXn
Crossbar
Port I/O
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