SI1012-A-GM Silicon Laboratories Inc, SI1012-A-GM Datasheet - Page 341
![IC TXRX MCU + EZRADIOPRO](/photos/14/21/142131/42-qfn-series_sml.jpg)
SI1012-A-GM
Manufacturer Part Number
SI1012-A-GM
Description
IC TXRX MCU + EZRADIOPRO
Manufacturer
Silicon Laboratories Inc
Specifications of SI1012-A-GM
Package / Case
42-QFN
Frequency
240MHz ~ 960MHz
Data Rate - Maximum
256kbps
Modulation Or Protocol
FSK, GFSK, OOK
Applications
General Purpose
Power - Output
13dBm
Sensitivity
-121dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
18.5mA
Current - Transmitting
30mA
Data Interface
PCB, Surface Mount
Memory Size
16kB Flash, 768B RAM
Antenna Connector
PCB, Surface Mount
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
240 MHz to 960 MHz
Interface Type
UART, SMBus, SPI, PCA
Output Power
13 dBm
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
4 mA
Minimum Operating Temperature
- 40 C
Modulation
FSK, GFSK, OOK
Protocol Supported
C2, SMBus
Core
8051
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
768 B
Supply Current (max)
4 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1871-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI1012-A-GMR
Manufacturer:
ROHM
Quantity:
12 000
- Current page: 341 of 384
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27.1.2. Mode 1: 16-Bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
27.1.3. Mode 2: 8-Bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If
Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal INT0
is active as defined by bit IN0PL in register IT01CF (see Section “12.6. External Interrupts INT0 and INT1”
on page 144 for details on the external input signals INT0 and INT1).
IN T 0
T 0
C ro ss b a r
P re -s ca le d C lo c k
S Y S C L K
IN 0 P L
G A T E 0
X O R
Figure 27.1. T0 Mode 0 Block Diagram
T R 0
0
1
M
H
T
3
M
T
3
L
C K C O N
M
H
T
2
M
T
2
L
0
1
M
T
1
M
T
0
S
C
A
1
S
C
A
0
Rev. 1.0
G
A
T
E
1
C
T
1
/
M
T
1
1
T M O D
M
T
1
0
T C L K
G
A
E
T
0
C
T
0
/
M
T
0
1
M
T
0
0
(5 b its )
T L 0
N
1
P
L
I
N
1
S
L
2
I
IT 0 1 C F
N
1
S
L
1
I
N
1
S
L
0
I
Si1010/1/2/3/4/5
N
P
0
L
I
(8 b its)
T H 0
N
S
0
L
2
I
N
S
0
L
1
I
N
S
0
L
0
I
T R 1
T R 0
T F 1
T F 0
IE 1
IE 0
IT 1
IT 0
Inte rru pt
341
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