XR17V352IB113-F Exar Corporation, XR17V352IB113-F Datasheet - Page 11

• Manufacturer Part Number: XR17V352IB113-F
• Description: IC UART PCIE 256B DUAL 113FPBGA
• Manufacturer: Exar Corporation

Specifications of XR17V352IB113-F

• Number Of Channels: 2, DUART
• Package / Case: 113-LFBGA
• Features: *
• Fifo's: 256 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 25 Mbps
• Supply Current: 120 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: BGA
• No. Of Pins: 113
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. 1.0.1
0x98-0xAF 31:0
0xB4-0xFF 31:0
A
O
0x100
DDRESS
0x8C
0xB0
0x80
0x84
0x88
0x90
0x94
FFSET
31:16
15:8
7:0
31:16
15:8
7:0
31:16
15:8
7:0
31:24
23:22
21:18
17:15
14:12
11:10
9:4
3:0
31:21
20
19
18
17:15
14:10
9:4
3:0
31:0
31:0
31:0
B
ITS
T
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
T
YPE
ABLE
1: PCI L
PCI Express 2.0 capable endpoint, Interrupt Message Number 1
Next Capability Pointer
PCI Express Capability ID
Not implemented or not applicable (return zeros)
Role-Based Error Reporting
256 bytes max payload size
Not implemented or not applicable (return zeros)
512 bytes max read request, Enable No Snoop
256 bytes max TLP payload size
Port Number
Not implemented or not applicable (return zeros)
Not implemented or not applicable (return zeros)
L1 Exit Latency < 1 us
L0s Exit Latency < 64 ns
Active State Power Management (ASPM) Support
L0s and L1 Supported
x1 max Link Width
2.5GT/s Link speed supported
Not implemented or not applicable (return zeros)
Data Link Layer Active Reporting capable
Surprise Down Error Reporting not supported
Reference clock must not be removed.
L1 Exit Latency - 2 us to less than 4 us
Not implemented or not applicable (return zeros)
x1 negotiated Link Width
Current Link Speed is 2.5GT/s
PCIe Capability Offset 0x14 - Slot Capabilities Register
Not implemented or not applicable (return zeros)
PCIe Capability Offset 0x30 - Link Status2/Control2
Not implemented or not applicable (return zeros)
VC Resource Capability Register
OCAL
B
US
C
ONFIGURATION
11
HIGH PERFORMANCE DUAL PCI EXPRESS UART
D
ESCRIPTION
S
PACE
R
EGISTERS
(
00000000000b
HEX OR BINARY
XR17V352
R
0x00040000
0x00000000
0x00010001
0x00000000
0x00010002
ESET
000001b
000001b
0x0202
0x0000
0x0000
00000b
0000b
0001b
0001b
0x80
0x28
0x10
000b
000b
010b
0x00
0x10
0x01
0x01
00b
11b
1b
0b
0b
V
ALUE
)