SST89V58RD2-33-C-NJE Microchip Technology, SST89V58RD2-33-C-NJE Datasheet - Page 20

• Manufacturer Part Number: SST89V58RD2-33-C-NJE
• Description: IC MCU 8BIT 40KB FLASH 44PLCC
• Manufacturer: Microchip Technology
• Series: FlashFlex®r

Specifications of SST89V58RD2-33-C-NJE

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-LCC (J-Lead)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 36
• Eeprom Size: 8K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: SST89xxxRD
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Data Sheet
SuperFlash Configuration Register (SFCF)
SuperFlash Command Register (SFCM)
SuperFlash Address Registers (SFAL)
SuperFlash Address Registers (SFAH)
©2007 Silicon Storage Technology, Inc.
Location
Location
Location
Location
B1H
B2H
B3H
B4H
Symbol
IAPEN
SWR
BSEL
Symbol
FIE
FCM[6:0]
Symbol
SFAL
Symbol
SFAH
FIE
7
7
7
7
-
IAPEN
FCM6
6
Function
Enable IAP operation
0: IAP commands are disabled
1: IAP commands are enabled
Software Reset
See Section 10.2, “Software Reset”
Program memory block switching bit
See Figures 3-1 and 3-2 and Table 3-2
6
Function
Flash Interrupt Enable.
0: INT1# is not reassigned.
1: INT1# is re-assigned to signal IAP operation completion.
Flash operation command
000_0001b Chip-Erase
000_1011b Sector-Erase
000_1101b Block-Erase
000_1100b Byte-Verify
000_1110b Byte-Program
000_1111b Prog-SB1
000_0011b Prog-SB2
000_0101b Prog-SB3
000_1001b Prog-SC0
000_1001b Prog-SC1
000_1000bEnable-Clock-Double
All other combinations are not implemented, and reserved for future use.
1. Byte-Verify has a single machine cycle latency and will not generate any INT1# interrupt regardless of FIE.
6
Function
Mailbox register for interfacing with flash memory block. (Low order address register).
6
Function
Mailbox register for interfacing with flash memory block. (High order address register).
External INT1# interrupts are ignored.
SuperFlash High Order Byte Address Register
SuperFlash Low Order Byte Address Register
FCM5
5
5
5
5
-
FCM4
4
4
4
4
-
1
20
FCM3
3
3
3
3
SST89V54RD2/RD / SST89V58RD2/RD
-
FCM2
2
2
2
2
-
FCM1
SWR
1
1
1
1
FCM0
BSEL
FlashFlex MCU
0
0
0
0
S71255-10-000
Reset Value
Reset Value
Reset Value
Reset Value
x0xxxx00b
00H
00H
00H
12/07