SST89V58RD2-33-C-NJE Microchip Technology, SST89V58RD2-33-C-NJE Datasheet - Page 36

• Manufacturer Part Number: SST89V58RD2-33-C-NJE
• Description: IC MCU 8BIT 40KB FLASH 44PLCC
• Manufacturer: Microchip Technology
• Series: FlashFlex®r

Specifications of SST89V58RD2-33-C-NJE

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-LCC (J-Lead)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 36
• Eeprom Size: 8K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: SST89xxxRD
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Data Sheet
4.2.4.7 Prog-SC0, Prog-SC1
Prog-SC0 command is used to program the SC0 bit. This
command only changes the SC0 bit and has no effect on
BSEL bit until after a reset cycle.
SC0 bit previously in un-programmed state can be pro-
grammed by this command. The Prog-SC0 command
should reside only in Block 1 or external code memory.
Prog-SC1 command is used to program the SC1 bit. This
command only changes the SC1 bit and has no effect on
SFCF[1] bit until after a reset cycle.
SC1 bit previously in un-programmed state can be pro-
grammed by this command. The Prog-SC1 command
should reside only in Block 1 or external code memory.
4.2.4.8 Enable-Clock-Double
Enable-Clock-Double command is used to make the MCU
run at 6 clocks per machine cycle. The standard (default) is
12 clocks per machine cycle (i.e. clock double command
disabled).
©2007 Silicon Storage Technology, Inc.
FIGURE
Program SC0 or SC1 -
Set-up Program SC0
indicates completion
MOV SFDT, #0AAH
MOV SFCM, #09H
MOV SFAH, #5AH
Polling SFST[2]
Polling scheme
4-7: Prog-SC0 and Prog-SC1
ORL SFCF, #40H
IAP Enable
Program SC0 or SC1 -
Set-up Program SC1
indicates completion
MOV SFAH, #0AAH
MOV SFDT, #0AAH
MOV SFCM, #89H
Interrupt scheme
INT1# Interrupt
1255 F14.0
36
4.2.5 Polling
A command that uses the polling method to detect flash
operation completion should poll on the FLASH_BUSY bit
(SFST[2]). When FLASH_BUSY de-asserts (logic 0), the
device is ready for the next operation.
MOVC instruction may also be used for verification of the
Programming and Erase operation of the flash memory.
MOVC instruction will fail if it is directed at a flash block that
is still busy.
4.2.6 Interrupt Termination
If interrupt termination is selected, (SFCM[7] is set), then
an interrupt (INT1) will be generated to indicate flash opera-
tion completion. Under this condition, the INT1 becomes an
internal interrupt source. The INT1# pin can now be used
as a general purpose port pin and it cannot be the source
of External Interrupt 1 during in-application programming.
In order to use an interrupt to signal flash operation termi-
nation. EX1 and EA bits of IE register must be set. The IT1
bit of TCON register must also be set for edge trigger
detection.
SST89V54RD2/RD / SST89V58RD2/RD
FIGURE
Program Enable-Clock-Double
indicates completion
MOV SFCM, #08H
Polling SFST[2]
Polling scheme
4-8: Enable-Clock-Double
Set-up Enable-Clock-Double
MOV SFDT, #0AAH
MOV SFAH, #55H
ORL SFCF, #40H
IAP Enable
Program Enable-Clock-Double
FlashFlex MCU
indicates completion
MOV SFCM, #88H
Interrupt scheme
INT1# Interrupt
S71255-10-000
1255 F15.0
12/07